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MPC7400 RISC Microprocessor Users Manual
60x Bus Signal ConTguration
8.2.4.1.2 Transfer Start (TS)Input
Following are the state meaning and timing comments for the TS input signal.
State Meaning
AssertedIndicates that another master has begun a bus transaction
and that the address bus and transfer attribute signals are valid for
snooping; see Section 8.2.4.5, òGlobal (GBL).ó
NegatedIndicates that no bus transaction is occurring.
Timing Comments
AssertionMay occur on any cycle following a qualiTed BG.
NegationMust occur one bus clock cycle after TS is asserted.
8.2.4.2 Transfer Type (TT[0:4])
The transfer type (TT[0:4]) signals consist of Tve input/output signals on the MPC7400.
For a complete description of TT[0:4] signals and for transfer type encodings, see
Section 9.3.2.2.1, òTransfer Type (TT[0:4]) Signals in 60x Bus Mode.ó
8.2.4.2.1 Transfer Type (TT[0:4])Output
Following are the state meaning and timing comments for the TT[0:4] output signals on the
MPC7400.
State Meaning
Asserted/NegatedIndicates the type of transfer in progress.
Timing Comments
Assertion/NegationThe same as A[0:31]
High ImpedanceThe same as A[0:31]
8.2.4.2.2 Transfer Type (TT[0:4])Input
Following are the state meaning and timing comments for the TT[0:4] input signals on the
MPC7400.
State Meaning
Asserted/NegatedIndicates the type of transfer in progress.
Timing Comments
Assertion/NegationThe same as A[0:31].
8.2.4.3 Transfer Burst (TBST)
Output
Unlike other processors that implement the 60x bus protocol, the transfer burst (TBST)
signal is an output-only signal on the MPC7400.
Following are the state meaning and timing comments for the TBST output signal.
State Meaning
AssertedIndicates that a burst transfer is in progress.
For transactions initiated by external control instructions (
eciwx
and
ecowx
), TBST forms part of the 4-bit Resource ID Teld on the bus as
follows:
TBST || TSIZ(0:2)
EAR(28:31)
NegatedIndicates that a burst transfer is not in progress.