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2.5.3 Using an External Clock
To use an external clock, connect a clock signal to the EXTAL pin and hold MODCLK low during reset.
Leave the XTAL and XFC pins floating, but connect VDDSYN to power. The frequency control bits in the
SYNCR register have no effect; the signal applied to the EXTAL pin should appear unchanged on the
CLKOUT line. The external clock must comply with the following expression.
Minimum external clock high/low time is a specification given in the device electrical characteristics.
2.6 Getting Out of Reset
Asserting and releasing the RESET line was once a relatively simple task. However, as microcontrollers
have become more complex, bidirectional reset pins have become standard. Bidirectional reset lines
allow an external device to reset the MCU and also allow the MCU to assert reset for associated pe-
ripherals. Bidirectional pins must be driven with open collector devices. A typical circuit for driving the
MCU RESET pin is shown in Figure 7. The RESET pin is driven by an open collector device, and it is
pulled to a logic 1 by an 820
resistor.
Figure 7 Typical MC68HC16Z1 Reset Circuit
When the internal PLL is used to generate the internal system clock, the RESET pin works as follows.
At power-up, the MCU drives RESET low. When the PLL locks, the MCU releases RESET for two sys-
tem clock cycles. If the external pull-up resistor can pull RESET to a logic 1 during the two cycles, the
MCU assumes that the reset is a power-on reset rather than an external reset. However, if RESET does
not rise to a logic 1 during the two cycles, the MCU assumes that the reset is an external reset and
drives RESET to a logic 0 for 512 clock cycles. After 512 cycles have elapsed, the MCU releases RE-
SET for 10 clock cycles. If RESET is a logic 1 at the end of the 10 cycles, the MCU begins program
execution. If RESET is a logic 0 at the end of the 10 cycles, the MCU once again actively drives RESET
low for 512 clock cycles. This cycle repeats until RESET is finally perceived to be at a logic 1. Figure 8 shows the waveform that is produced on the RESET line when the pull-up resistor is too large and pull-
up current is inadequate.
Minimum external clock period
Minimum external clock high/low time
50%
percentage variation of external clock input duty cycle
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332TUT LVI/RESET CONN
RESET
O.C.
MC68HC16Z1
LOW VOLTAGE
INHIBIT DEVICE
+5V
10K
820
10–100
F
+5V
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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