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| 型號(hào)： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
pins is recognized as a valid interrupt request if the interrupt priority level of the pin is greater than the
value of the IPL field in the condition code register (CCR). Once an interrupt service request is recog-
nized, the CCR is copied onto the stack, then the IPL value is changed to match the priority level of the
interrupt being serviced. This prevents interrupts of the same or lower priority while the service routine
executes. For instance, if the IPL value is $3, and a level five service request is recognized, the CCR is
stacked, then the IPL value is changed to $5. An RTI instruction at the end of the service routine nor-
mally terminates interrupt service. RTI pops the stacked CCR, and thus restores the original IPL value.
The IPL field can also be changed by writing to the CCR. If an interrupt service routine writes a lower
value to the IPL field while the request signal is still asserted, the CPU recognizes a second service
request.
IRQ7 is both edge and level sensitive. Level seven interrupts cannot be masked by the IPL field. When
a level seven interrupt service request is recognized, the current value of the condition code register is
pushed onto the stack, and the IPL value is changed to $7.
It is very important to make certain that the IRQ7 signal be negated before the level seven interrupt ser-
vice routine ends. A new level seven interrupt will be recognized in the following cases:
If the IRQ7 signal negates and is then re-asserted while the interrupt service routine is executing.
If the IRQ7 signal remains asserted through the execution of the RTI instruction that ends the ser-
vice routine.
If the IRQ7 signal is asserted and the IPL field is written during execution of the interrupt service
routine. This is true even when the mask is re-written to $7.
Provide for negation of the signal within the service routine, and avoid writing to the CCR during execu-
tion of the level seven interrupt service routine.
2.10.6 Checklist for External Interrupt Acknowledge
Is the desired pin configured as an interrupt pin instead of an I/O pin?
The interrupt pins are dual-function pins. Their initial configuration is determined by the state of data
bus pin 9 at the release of reset. After reset, their configuration is determined by the port F pin assign-
ment register.
Was the starting address of the interrupt routine written to the vector offset address?
The CPU must be told where the interrupt service routine begins. See 4.1.2 Exceptions for a more de-
tailed explanation.
Is the IARB field in the SIMCR a unique, non-zero value between $1 and $F?
All interrupting modules must have a unique, non-zero value in the IARB field.
Is the IPL field in the condition code register set to a value lower than the desired interrupt lev-
el?
The CPU will not recognize an interrupt that is at the same level or lower than the value in the IPL field.
Level 7 is the only exception to this rule; it is always recognized.
Is the IACK cycle terminated with AVEC or DSACK?
The IACK cycle must be terminated by assertion of the AVEC or DSACK signals, or a chip-select circuit
must be configured to assert AVEC or DSACK internally.
Does the interrupt request signal negate inside the exception handler?
It is a good idea to control negation of the interrupt in software. The interrupt should be negated before
the RTI instruction.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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