參數(shù)資料
型號(hào)： MC68HC16Z1VEH16
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 16/56頁(yè)
文件大?。?/td> 0K
描述： IC MCU 16BIT 1K FLASH 132-PQFP
標(biāo)準(zhǔn)包裝： 36
系列： HC16
核心處理器： CPU16
芯體尺寸： 16-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤(pán)
Figure 14 Configuring 16-Bit Memory with 8-Bit RAMs — Separate Read and Write Enables
2.10 Using External Interrupts
The MCU has seven external interrupt lines, IRQ[7:1]. These are active low signals that cause the pro-
cessor to jump to a special routine and then return to the main code. The following paragraphs cover
the basic elements of servicing external interrupt service requests. Refer to 4.1.2 Exceptions for more
detail. Chapter 6 of the
SIM Reference Manual (SIMRM/AD) has an in-depth explanation of how to use
external interrupts.
2.10.1 Interrupt Priority Levels
An interrupt can be recognized on one of seven priority levels. These levels correspond to the numeric
values of the external interrupt request lines. Level one (IRQ1) has the lowest priority; level seven
(IRQ7) has the highest priority level. Levels one through six can be masked by the interrupt priority level
(IPL) field contained in bits 7 through 5 of the condition code register (CCR). The level specified in the
IPL field and all levels below it are masked and are not recognized by the CPU. Level 7 is the only ex-
ception to this rule; it cannot be masked. Out of reset, the IPL field is set to level 7. Thus, levels 1 through
6 will not be recognized unless the IPL field is re-written to a lower value. The priority mask value can
be changed by writing a new value into the appropriate bits of the CCR.
EXAMPLE:
To allow interrupts on levels 6 and 7 only, mask out levels 5 and below.
ANDP #$FF1F
ORP #$00a0
During interrupt processing, a copy of the current CCR is saved onto the stack, and the priority level of
the interrupt being serviced is written to the IPL field of the CCR. This means that during execution of
an interrupt routine, only higher priority interrupts can be recognized. However, the CPU16 guarantees
that at least the first instruction of an interrupt routine will be executed before another interrupt can pre-
empt it. This allows the interrupt routine to inhibit other interrupts (except for level 7) during the routine
by re-writing the IPL field in the CCR.
332TUT EXT MEM CONN 3
MCU
ROM ENABLE
ADDR[16:1]
DATA
RAM
32K X 8
ROM
32K X 16
CE
ADDR[13:1]
DATA[7:0]
DATA[15:0]
ADDR
DATA
ADDR
DATA
RAM
32K X 8
ADDR[13:1]
WE
DATA[15:8]
ADDR
CE
LOWER BYTE ENABLE
UPPER BYTE ENABLE
ADDR[16:0]
DATA[15:0]
CS0
CS1
CSBOOT
CS2
OE
READ ENABLE (BOTH BYTES)
WE
CE
OE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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