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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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high. Conditioning RESET with R/W and DS ensures that writes to external memory will be completed
before the 74HC244s are enabled. Otherwise, if an external RESET signal was applied during a write
to external memory and was not conditioned with R/W and DS, the 74HC244s would turn on during the
write and cause data bus contention.
Figure 1 Circuitry to Drive Data Bus Pins During RESET Assertion
There are several alternative methods of driving data bus pins low during reset. The easiest methods
are to connect a resistor in series with a diode from the data bus pin to the RESET line or to connect a
transistor, as shown in Figure 2. When using a bipolar transistor, a base current limiting resistor is re-
quired. When using field effect transistor, a base limiting resistor is not needed. However, the best meth-
od is to use the configuration shown in Figure 1.
Figure 2 Alternate Methods of Conditioning Data Bus Pins
2.2 Choosing Memory Width
One decision that must be made early in the design is the width of memory to be used. Systems with
8-bit wide memory, 16-bit wide memory or a combination of the two can be implemented using only the
D15
D8
D7
D0
74HC244
RESET
DS
R/W
OE
IN1
IN8
OUT1
OUT8
IN1
IN8
OUT1
OUT8
820
10K
10K
+5V
MC68HC16Z1
332TUT DAT PIN RESET
TIE INPUTS
HI OR LO
AS NEEDED
TIE INPUTS
HI OR LO
AS NEEDED
332TUT DAT RESET HOLD
1K
1N4148
DATA PIN
RESET
2K
DATA PIN
RESET
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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