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參數(shù)資料
| 型號(hào)： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 37/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
* The next commands set the control parameters. Interrupts are not enabled. To
* enable interrupts upon assertion of the SPIF bit, set SPCR2[15]. To clear
* an interrupt, read and then clear the SPIF bit. Wrap-around mode is enabled.
* NEWQP is set to zero, and ENDQP is set to $F. Thus, the QSPI will
* continuously transmit the data between $0 and $F in the queue. To disable
* wrap-around mode so that the QSPI only goes through the queue once, clear the
* WREN bit (SPCR2[14]) to a zero.
LDD #$4F00
STD SPCR2
;NEWQP=0, ENDQP=$F, WREN is enabled
STAB SPCR3
;Disable loop mode, HALTA and MODF
;interrupts, and HALT.
LDX #DATA
;Point X to the data to be transmitted.
LDY #TR0
;Point Y to the transmit data RAM.
LDZ #CR0
;Point Z to the command RAM
LDE #$10
;Set a counter to count down from 16 ($10),
;since there are 16 queue entries to fill.
LOOP:
LDD 0,X
STD 0,Y
;Begin a loop to fill the transmit RAM.
AIX #$02
;Store the data right-justified.
AIY #$02
* The next commands fill the command RAM in a right-justified manner. There is
* one byte of control information for each QSPI command to be executed in the
* queue. Here, all four chip selects will drive low during each serial transfer.
CLRB
STAB 0,Z
INCZ
;fill command RAM: chip selects active low
SUBE #$01
;Subtract one from the counter
BNE LOOP
;Fill next queue entry if not done
LDD #$8000
STD SPCR1
;Begin operation by setting the SPE bit.
FINISH:
BRA FINISH
;Normally, this would begin the next task.
INT:
RTI
;unused interrupts will jump here
DATA
DB 16
;Set aside memory space for the data to be
;transmitted. This program does not
;initialize the data.
4.4.3 Initializing QSM Interrupts
To enable interrupts on the QSM, initialize the following five fields:
1. ILPQSPI and ILSCI in the QILR register determine the priority levels of QSPI and SCI interrupts,
respectively. If the fields are set to the same level, the QSPI takes priority.
2. INTV[7:0] in the QIVR register determines the interrupt vector number. For the QSPI, the least
significant bit is read as a one, and for the SCI, the least significant bit is read as a zero.
3. IARB in the QMCR register determines precedence if the QSM and another module simulta-
neously make an interrupt service request of the same priority. This field must be initialized to a
unique, non-zero value if interrupts are enabled.
4. IPL in the CPU condition code register determines the priority level at which interrupts are rec-
ognized. In order for QSM interrupts to be recognized, this field must be given a value that is
lower than the interrupt priority level specified in the QILR register.
5. The interrupt vector tells the processor where to find the interrupt service routine. Store the start-
ing address of the service routine in the interrupt vector table at the appropriate vector offset ad-
dress. The vector offset address is equal to (interrupt vector number X 2).
4.5 Configuring the General-Purpose Timer
The general-purpose timer (GPT) is a software-interrupt driven timer that is very similar to the timer
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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