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| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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4.2 Configuring the System Integration Module
Since the SIM determines important operating characteristics of the entire MCU, it should be the first
module after the CPU to be initialized. The following paragraphs discuss registers important to initial
configuration.
4.2.1 System Integration Module Configuration Register (SIMCR)
The SIMCR controls module mapping for the MCU, internal use of the FREEZE signal, and the prece-
dence of simultaneous interrupt requests of the same priority. Configure the SIMCR as follows.
Leave the state of the module mapping (MM) bit at its reset state of one. MM determines where the in-
ternal control registers are located in the system memory map. When MM = 0, register addresses range
from $7FF000 to $7FFFFF; when MM = 1, register addresses range from $FFF000 to $FFFFFF. How-
ever, since the CPU16 cannot access addresses $080000 to $7FFFFF, do not change the MM bit to
zero.
1. If using the software watchdog, periodic interrupt timer, or the bus monitor, select action taken
when FREEZE is asserted. The freeze software enable (FRZSW) bit determines whether the
software watchdog and periodic interrupt timer counters continue to run when FREEZE is assert-
ed, and the freeze bus monitor enable (FRZBM) bit determines whether the bus monitor contin-
ues to operate when FREEZE is asserted.
2. Select the interrupt arbitration level for the SIM with the interrupt arbitration (IARB) field. The de-
fault state out of reset is $F, the highest precedence. To avoid spurious interrupts, each module
requesting interrupts must have a unique, non-zero value in the IARB field. The CPU treats ex-
ternal interrupt requests as SIM interrupts.
4.2.2 Clock Synthesizer Control Register (SYNCR)
SYNCR controls clock frequency, clock signal usage during low-power stop, and frequency of the 6800
bus clock output (ECLK). Configure SYNCR as follows.
Set frequency control bits (W,X,Y) to specify frequency.
1. Select action to be taken during loss of crystal (RSTEN bit): activate a system reset or operate
in limp mode.
2. Select system clock during LPSTOP (STSIM and STEXT bits).
3. If using the ECLK, select the ECLK frequency (EDIV bit).
4.2.3 System Protection Control Register (SYPCR)
SYPCR controls the software watchdog, which is enabled out of reset. This means that, unless the SWE
bit is cleared, a program must write the appropriate service sequence to the software service register
(SWSR) in a defined period or the MCU will reset each time the watchdog times out.
Disable the software watchdog, if desired, by clearing the SWE bit.
1. If the watchdog is enabled, perform the following actions.
A.Choose whether to prescale the software watchdog clock (SWP bit).
B.Select the time-out period (SWT bits).
2. Enable the double bus fault monitor, if desired (DATAFE bit or HME bit).
3. Enable the external bus monitor (BME bit) if desired.
4. Select the time-out period for bus monitor (BMT bits).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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