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| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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Figure 15 Chip-Select Line Used for Interrupt Acknowledge
2.10.4.2 Autovectors
When an external device cannot supply a vector number in response to an IACK cycle, an autovector
can be used instead. The autovector number is determined by the priority of the interrupt request. For
example autovector number 2 corresponds to IRQ2. In order for an autovector to be automatically used,
the IACK cycle must be terminated by an AVEC signal. There are two ways to do this: either assert the
AVEC signal externally or use the internal chip-select circuitry to provide the AVEC signal. Once the
bus cycle has been terminated, the CPU saves the current context, loads the 16-bit vector into the PC,
and begins to execute the service routine at that address. As a side note, internal modules cannot ter-
minate an IACK cycle with AVEC, which would cause the CPU to automatically provide the autovector.
An internal module must request a particular vector number by writing the appropriate value to its inter-
rupt configuration register. The internal module will then automatically terminate the IACK cycle with
DSACK and provide the CPU with the vector number as specified by its interrupt configuration register.
One way to use autovectors is to tie the AVEC pin to ground. This effectively generates an external
AVEC signal only in response to all IACK cycles caused by external interrupt service requests. If it is
not desirable for all external interrupts to autovector, specific external devices can assert AVEC in re-
sponse to an IACK cycle. However, in this case it is usually easier to set up a chip-select circuit to pro-
vide the AVEC signal internally.
Perform the following steps to set up a chip-select circuit to generate the AVEC signal:
1. Configure the chip-select pin for any of its available functions in the pin assignment register.
2. Program the appropriate base address register to $FFF8 or higher.
3. Select the following fields in the appropriate option register:
A.MODE Bit — select asynchronous mode (%0)
B.BYTE Field — select assertion for both bytes (%11)
C.R/W Field — select assertion for both reads and writes (%11)
D.STRB Bit — select synchronization with AS (%0)
E.DSACK Field — select number of wait states (user specified)
F.SPACE Field — select CPU space assertion (%00)
G.IPL Field — select interrupt priority level (user specified)
H.AVEC Bit — enable AVEC generation (%1).
See 4.2 Configuring the System Integration Module for a more detailed description of the fields in
chip-select option registers.
2.10.5 Level-Sensitive versus Edge-Sensitive Interrupt Pins
Interrupt pins IRQ[6:1] are level sensitive. Assertion of an active-low signal connected to one of these
332TUT PERI CONN
CS
D7
D0
IACK
D15
D8
CS0
CS1
MC68HC16Z1
PERIPHERAL
D6
D14
D5
D13
D4
D12
D3
D11
D2
D10
D1
D9
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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