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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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used extensively on the M68HC11 series of microcontrollers. Because the GPT uses design rules for
the M68300 family, the GPT runs four times faster on the M68300/M68HC16 families than it does on
the M68HC11 family. While the GPT does reside on the intermodule bus, it does not have a self con-
tained arithmetic logic unit or RISC-like microengine (like the time processor unit on other modular
MCUs) with specialized instruction sets. The GPT functions are briefly described below. For a more de-
tailed explanation, refer to the
GPT Reference Manual (GPTRM/AD).
Input Capture Pins (IC[1:3]): Each of these pins is associated with a single input capture function and
has a dedicated 16-bit capture register to hold the captured counter value. These pins can also be con-
figured for general-purpose I/O.
Output Compare Pins (OC[1:4]): Each of these pins has a dedicated 16-bit compare register and a
16-bit comparator. Pins OC2, OC3, and OC4 are associated with a specific output compare function,
whereas the OC1 function can affect the output of any combination of output compare pins. Automatic
preprogrammed pin actions occur on a successful match. The OC1 pin can alternately be used to output
the clock selected for the timer counter register (TCNT). Also, any of the pins can be used for general-
purpose I/O.
Pulse Accumulator Input Pin (PAI): The pulse accumulator counter (PACNT) is an 8-bit read/write up
counter register that can operate in an external event counting or gated time accumulation mode. The
user software can write the number of edges to be counted to the PACNT register. As the edges are
counted, the counter will approach $FF, roll over to $00, and generate an interrupt. The pulse accumu-
lator overflow flag will indicate that the count has rolled over.
Pulse-Width Modulation (PWMA, PWMB): These are the outputs to the two PWM functions. They can
be programmed to generate a periodic waveform with a variable frequency and duty cycle. Alternately,
these pins can be used for general-purpose I/O. PWMA can also be used to output the clock selected
as the input to the PWM counter (PWMCNT).
Auxiliary Timer Clock Input (PCLK): This is an external clock input dedicated to the GPT that can be
used as the clock source for the capture/compare unit or the PWM unit in place of one of the prescaler
outputs. If this pin is not used as a clock input, it can be used as a general-purpose input pin.
General-Purpose I/O: Many of the GPT pins can be used as general-purpose I/O. All that is needed to
configure a pin to general purpose I/O is to select the data direction in the data direction register (called
PDDR in older manuals and DDRGP in newer manuals) and the actual data in the data register (called
PDR in older manuals and PORTGP in newer manuals). Take special care when writing data to the data
register, since a read of this register returns the actual pin state and not the data just written to it. Beware
of the following scenario:
The current value of PORTGP is $FF. The user software wishes to clear bit 0 and then OR this bit with
a value in another register, which also happens to be zero. Thus, the end result should be $FE. To ac-
complish this, the software does a BCLR instruction immediately followed by an OR instruction. How-
ever, there is a good probability that after the BCLR instruction, the pin state will not have changed by
the time the CPU reads PORTGP again for the OR instruction. Thus, the CPU could read the value $FF
from PORTGP instead of $FE and end up with the wrong result. To avoid this scenario, put a NOP or
a different instruction between two read-modify-write instructions involving the PORTGP register.
4.5.1 GPT Interrupts
Several steps must be followed in order for a GPT channel to request interrupt service.
1. Store the starting address of the interrupt service routine in the CPU interrupt vector table.
The location in the vector table where the service routine starting address is stored is called the
vector address. The vector address is calculated from the interrupt vector number — the address
is two times the vector number.
The interrupt vector number is formed by concatenating a base vector number with the vector
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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