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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
LDE #$0005
;counter that will count to end of message
* The next three commands check to see if the transmit data register is empty
* by looking at the TDRE bit in the SCI status register (SCSR).
If the TDRE bit
* is zero, then there is data in register TDR that has not yet been sent to the
* transmit serial shifter. If the TDRE bit is one, then the transfer has
* occurred, and a new character may be written to register TDR. Thus, this
* sequence of code loops until the TDRE bit is one.
LOOP
LDAB
0,X
;1st char in accumulator B
CHAR
LDAA
SCSR
;see if TDRE bit in SCI Status Register is
ANDA
#$01
;set
BEQ
CHAR
;wait until it is
LDAA
SCSR
ANDA
#$FE
STAA
SCSR
;clear TDRE bit
CLRA
STD
SCDR
;store char to be printed in data register
AIX
#1
;point to next char
SUBE
#$01
BNE
LOOP
;loop to print next char
FINISH
BRA
FINISH
;stay here when done
INT
RTI
;unused exceptions point here
MESSAGE
FCB
'12345'
;“12345” will be printed
4.4.2 Configuring the QSPI
The QSPI uses a synchronous serial bus to communicate with external peripherals and other MCUs.
The QSPI serial protocol is compatible with the serial peripheral interface (SPI) on the M68HC11 and
M68HC05 families of MCUs. The module also has a queue, programmable queue pointers that allow
up to 16 automatic transfers, and a wrap-around mode that allows continuous transfers to and from the
queue with no CPU intervention. The queue is useful in applications such as control of an A/D converter.
Remember the following points when using the QSPI:
Setting the SPE bit to enable the QSPI should be the last step in initialization.
Data direction register DDRQS and port data register PORTQS must be initialized, even for pins that
are assigned to the QSPI in pin assignment register PQSPAR.
Peripheral chip-select signals are asserted when a command in command RAM is executed, but the
assertion state (active high or active low) of the peripheral chip-select signal is determined by the val-
ue of the appropriate bit in PORTQS.
Take special care when writing PORTQS since a read of this register returns the actual pin state and
not the data just written to it. Beware of the following scenario:
The QSPI is inactive, and the current value of PORTQS is $FF. The user software wishes to clear bit
0 and then OR this bit with a value in another register, which also happens to be zero. Thus, the end
result should be $FE. To accomplish this, the software does a BCLR instruction immediately followed
by an OR instruction. However, there is a good probability that after the BCLR instruction, the pin state
will not have changed by the time the CPU reads PORTQS for the OR instruction. Thus, the CPU
could read the value $FF from PORTQS instead of $FE and end up with the wrong result. To avoid
this scenario, put a NOP or a different instruction between two read-modify-write instructions involving
the PORTQS register.
Take special care when writing PORTQS while using the QSPI because control of the PORTQS pins
is shared by the QSPI and the CPU. During transfers, the QSPI controls the pins assigned to it in the
PQSPAR, but when transfers are complete, control reverts to what the CPU has written in PORTQS.
Beware of the following scenario:
The CPU writes the initial value of PORTQS to $FF, so that the inactive state of each QSPI chip select
pin is high. The CPU configures the active state of each chip select to be low in the command RAM.
Later, the user software decides to make PCS1 (bit 4 in PORTQS) drive low all of the time. To do this,
it arbitrarily does an AND of PORTQS with $EF to clear bit 4 without affecting any other bits in the
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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