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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
byte-wide devices is simple. Use a separate chip-select pin for each device, and configure chip-select
logic to decode the upper and lower bytes, respectively. Each of the chip-select circuits must be config-
ured as a 16-bit port, even though only eight bits of memory are being accessed. This allows both byte
and word writes — if both memories were connected to the same chip-select line, byte writes would
corrupt the adjacent byte. This function can also be implemented in external logic by gating a single
chip-select line with the MCU ADDR0 line to select upper and lower bytes. For ROM memory a single-
chip-select can be used to enable both byte-wide ROMs, as the MCU uses only the required byte on
the data bus during a byte read and ignores the remaining byte.
Figure 13 illustrates how to connect two 8-bit memories as one 16-bit port. It also shows the connec-
tions necessary for a 16-bit memory. In this example configuration, CS0 is connected to the chip enable
pin CE of the first RAM chip and CS1 is connected to the chip-enable pin of the second RAM chip. This
effectively makes CS0 the upper byte enable and CS1 the lower byte enable. The R/W line of the MCU
is connected to the R/W lines of both RAM chips. CSBOOT is connected to the ROM enable. AD-
DR[13:1] of the MCU are connected to address lines [12:0] of each RAM chip, and ADDR[16:1] of the
MCU are connected to address lines [15:0] of the ROM.
Figure 13 Configuring 16-Bit Memory with 8-Bit RAMs — Common R/W Input
Another common configuration is shown in Figure 14. Here, the chip enables (CE) are always asserted,
the write enable (WE) for upper byte access is connected to CS0, the write enable for lower byte access
is connected to CS1, and the read enable (OE) for both upper and lower byte accesses are connected
to CS2. See 4.2.10 Example of SIM Initialization for software to initialize this example system.
332TUT EXT MEM CONN 2
MCU
ROM ENABLE
ADDR[16:1]
DATA
RAM
32K X 8
ROM
32K X 16
CE
ADDR[13:1]
R/W
DATA[7:0]
DATA[15:0]
ADDR
DATA
ADDR
CE
DATA
RAM
32K X 8
ADDR[13:1]
R/W
DATA[15:8]
ADDR
CE
LOWER BYTE ENABLE
UPPER BYTE ENABLE
ADDR[16:0]
DATA[15:0]
R/W
CS0
CSBOOT
CS1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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