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| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 17/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標準包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
2.10.2 Interrupt Arbitration Field
Most modules in the MCU can request interrupt service. The CPU treats external interrupts as interrupt
service requests from the system integration module (SIM). The interrupt arbitration (IARB) field in the
configuration register of each module determines which module's interrupt requests take precedence
when the CPU receives more than one request at the same priority level. In order for interrupt requests
to be acknowledged, each module must be assigned a unique IARB number between $1 (lowest pre-
cedence) and $F (highest precedence). Out of reset, the SIM IARB field has an initial value of $F, while
other modules have initial IARB values of $0.
2.10.3 Interrupt Vectors
Vectors are 16-bit addresses that point to the interrupt service routines (and other exception handlers).
They are stored in a data structure called the exception vector table. There are 256 vector addresses
in the exception vector table; of these, 199 can be used for interrupts. The base address of the excep-
tion vector table is determined by the value stored in the vector base register. A vector number is used
to calculate the vector address, i.e., a displacement into the exception vector table.
2.10.4 The Interrupt Acknowledge Cycle
After the CPU recognizes a valid interrupt request, the CPU begins the interrupt acknowledge (IACK)
cycle. The CPU changes the IPL mask value to the level of the acknowledged interrupt to preclude low-
er-or-equal priority interrupt requests, then initiates a read cycle in CPU space. Since there is no dedi-
cated IACK pin on the MCU, an external IACK signal is usually provided by a chip-select pin.
Vector numbers can be supplied by the device requesting interrupt service, or they can be generated
automatically. Vector numbers supplied by the device cause the CPU to access one of 192 user vectors
in the exception vector table; automatically generated vectors cause the CPU to access one of the 7
autovectors in the table. Each method of vector number acquisition requires a different form of IACK
cycle termination. If a vector number is supplied, either the requesting device must terminate the IACK
cycle with a DSACK signal or the chip-select logic must generate the DSACK signal internally. If an au-
tovector is used, an external device can assert the AVEC signal or an AVEC signal can be generated
by the chip-select logic. Since normal bus cycles occur in user or supervisor space, but an IACK cycle
occurs in CPU space, the same chip-select circuit cannot be used to terminate both an IACK cycle and
a normal bus cycle.
2.10.4.1 User Vectors
Once an interrupting device has placed a user vector number on the external data bus in response to
an IACK signal from the MCU, either the device must terminate the IACK cycle with DSACK, or the chip-
select logic must generate DSACK internally. When the bus cycle has been terminated, the vector num-
ber is left-shifted once (multiplied by 2) to form the 16-bit vector address. The CPU then saves the cur-
rent context, loads the 16-bit vector into the PC, and begins to execute the service routine at that
address.
An example is shown in Figure 15. Chip select 1 is configured for interrupt acknowledge and automatic
generation of the DSACK signal. It is connected to the IACK pin of the peripheral. Because the proces-
sor drives $FFFFFx onto the address bus and drives the function code pins to indicate CPU space dur-
ing an IACK cycle, the chip-select base address register must be programmed to $FFFX. When the
CPU recognizes an interrupt and initiates an IACK cycle, CS1 is asserted. In response, the peripheral
drives an 8-bit vector number onto the data bus. Chip-select logic then terminates the IACK cycle with
DSACK.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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