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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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crease the number of holes connecting to the supply planes, they should be used only as a last resort.
Localize any high frequency circuits, such as the clock and address or data buses. Decouple locally
using high frequency filters such as ferrite chokes or damping resistors. Be sure to separate the high
speed and low speed circuits.
Turn off any output signals (such as ECLK) that are not used.
Shield the board externally.
Reduce power supply noise as much as possible.
2.8.3 Other Sources of Information
Freescale publishes two application notes on related subjects:
Designing for Electromagnetic Compatibility with HCMOS Microcontrollers (AN1050)
Transmission Line Effects in PCB Applications (AN1051).
EDN Magazine offers a reprint of the “Designer’s Guide to Electromagnetic Compatibility.”
Refer to 6 Sources of Information for ordering information.
EMC consultants are probably the best source of information on this topic, since they specialize in EMC
and RFI problems. Consultants can help troubleshoot real problems, conduct seminars, and provide tu-
torials, books and software on the subject.
2.9 Connecting Memory and Peripherals
The MCU offers many different ways to configure memory and peripherals. The user can decode the
external bus interface externally or use chip-selects. Since it is usually more efficient to use the chip-
selects, this tutorial does not cover signal decoding. However, the
SIM Reference Manual (SIMRM/AD)
gives detailed explanations and examples of how to decode signals for both 8- and 16-bit memory de-
vices on pages 5-31 through 5-34. These examples also show how to use function code pins to deter-
mine which address space is being accessed.
The MC68HC16Z1 can generate 12 chip-select signals. These signals can be used to expand the sys-
tem. A chip-select signal selects and enables a particular peripheral device or memory chip for data
transfer. The chip-select circuits can also be programmed to generate data transfer and size acknowl-
edge (DSACK), interrupt acknowledge (IACK), and autovector (AVEC) signals.
2.9.1 Using Chip-Selects to Generate DSACK
Chip-select circuits can be configured to wait for external data and size acknowledge signals on the
DSACK1 and DSACK0 lines or to generate internal DSACK signals. A circuit can generate an internal
DSACK signal even if the pin is configured for discrete output or alternate function.
The chip-select logic can wait for a certain number of clock states before generating DSACK. These
states are called wait states. Wait states are inserted after state 3 of a read or write bus cycle. A normal
bus cycle lasts three clock cycles plus the number of wait clock cycles. The chip-select logic can insert
a maximum of 13 wait states.
2.9.1.1 The Relationship Between Wait States and Memory Speed
Memory speed and the number of wait states necessary are related by the following equations:
Address access time = (2.5 + WS) X tCYC(min) - tCHAV(max) - tDICL(min)
Chip-select access time (MCU read cycle) = (2 + WS) X tCYC(min) - tCLSA(max) - tDICL(min)
Chip-select access time (MCU write cycle) = (2 + WS) X tCYC(min) - tCLSA(max) + tCLSN(min)
In the equations, WS is the number of wait states programmed in the DSACK field. For fast termination
mode, WS = –1, for zero wait states, WS = 0, for one wait state, WS = 1, etc. Also, it is assumed that
chip-select assertion is based on address strobe. If it is based on data strobe, add 2(tCYC) to tCLSA for
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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