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| 型號(hào)： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 39/56頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
number given in Table 7-1 on page 7-3 in the
GPT Reference Manual (GPTRM/AD). As shown
in Table 7-1, each timer channel has a separate vector number. Choose a base vector number
and write it to bits [7:4] in the GPT interrupt configuration register (ICR). For example, choosing
a base vector number of $81 would assign interrupt vector $80 to input capture 1, interrupt vector
$82 to input capture 2, interrupt vector $83 to input capture 3, and so on, through assignment of
interrupt vector $8B to pulse accumulator input flag.
For example, if output compare 1 is being set up to request interrupt service, the interrupt vector
is $84. The vector address is:
2
$84 = $108
Thus, the starting address of the interrupt routine must be stored in location $108.
2. Store an interrupt priority level for the GPT in bits [10:8] of the ICR.
This value determines the priority of GPT interrupt service requests. The value must be a number
between 1 and 7 — level 7 has the highest priority, and level 1 has the lowest. The value stored
in the IPL field in the CPU condition code register determines whether an interrupt request is rec-
ognized. The value in the IPL field must be lower than the GPT interrupt priority level in order for
the GPT to interrupt the CPU, unless the interrupt level is seven, in which case it cannot be
masked.
3. If desired, specify which interrupt source within the GPT has the highest priority by writing to bits
[15:12] of the ICR.
This value determines which interrupt source within the GPT has the highest priority. As Table
7-1 on page 7-3 in the
GPT Reference Manual (GPTRM/AD) shows, each interrupt source within
the GPT is pre-assigned a priority. However, the user can pick one of those sources to have the
highest priority. For example, if a $4 is written to bits [15:12] of the ICR, then OC1 will have the
highest priority. When OC1 generates an interrupt, the low nibble of the vector will be $0 instead
of $4. The remaining channels maintain their original relative priority and vector addresses.
4. Store an interrupt arbitration value in the IARB field of the GPT module configuration register.
The IARB field value determines precedence when the CPU receives more than one interrupt
request of the same interrupt priority level. Each interrupting module must be assigned a unique
IARB number between $01 (lowest precedence) and $0F (highest precedence).
5. Set the interrupt enable bit for the channel in the timer interrupt mask register (TMSK1/TMSK2).
This simply involves writing the channel's bit number to a one.
To clear an interrupt, negate the appropriate interrupt status flag in the timer interrupt flag regis-
ters (TFLG1/TFLG2). Read the flag in the asserted state and then write a zero to the bit. As long
as the interrupt status flag is set, the channel will continue to request interrupts.
4.5.2 GPT Initialization Example
The following example uses all five output compare channels. In this example, OC1 controls the OC1,
OC2, and OC3 pins. OC4 and OC5 operate independently. The period of OC[1:3] is $200 TCNTs. The
period of OC4 is $400, and the period of OC5 is $800. The frequency of TCNT is the system clock di-
vided by four. Therefore, for a 16.778 MHz system clock, each TCNT tick is 238 ns long. Thus, the pe-
riod of OC[1:3] is approximately 122
s, and the periods of OC4 and OC5 are approximately 244 s and
488
s, respectively.
This example is in the file “gpt_init.asm” in the archive “16Z1_init” on the Freeware Data System.
INCLUDE
'EQUATES.ASM'
;register addresses
INCLUDE
'INIT_RES.ASM'
;initialize reset vector
INCLUDE
'INIT_INT.ASM'
;initialize interrupt vectors
ORG
$200
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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