參數(shù)資料
型號： MC68HC16Z1VEH16
廠商： Freescale Semiconductor
文件頁數(shù)： 40/56頁
文件大?。?/td> 0K
描述： IC MCU 16BIT 1K FLASH 132-PQFP
標(biāo)準(zhǔn)包裝： 36
系列： HC16
核心處理器： CPU16
芯體尺寸： 16-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
INIT_SIM:
LDAB
#$0F
;set EK to $F to point to internal regs
TBEK
LDAA
#$7F
;increase clock speed to 16.778 MHz,
STAA
SYNCR
;assuming a 32 kHz crystal and using the VCO
CLR
SYPCR
;disable software watchdog
ANDP
#$FF1F
ORP
#$00A0
;allow interrupts on levels 6 and 7
INIT_GPT:
LDD
#$FF00
STD
PDDR
;make all GPT pins outputs
LDD
#$0000
;set I4/O5 pins to output compare
STD
PACTL
;(this is the default value)
LDD
#$3800
;set up value for OC1M/OC1D: OC1 controls
STD
OC1M
;OC1-3, data = 0 at match
* TOC1 works differently than the other four OC channels because it can
* control all five OC channels. Here, it is configured to affect only the
* OC1 - OC3 channels. OC1 does not have the ability to toggle on a match.
LDD
TCNT
;add offset to TCNT for delay before
ADDD
#$200
;first compare
STD
TOC1
;store TCNT + Offset into TOC1
STD
TOC4
;store TCNT + Offset into TOC4
STD
TI4O5
;store TCNT + Offset into TOC5
* All of the OC channels are initialized with the same value so that
* the 5 square waves will be phase locked. Different offsets could be used
* for each channel. This would simply skew the square waves with respect
* to each other; they would still be frequency locked.
LDD
#$5000
STD
TCTL1
;OC 4 and 5 will toggle on compare
INIT_INTS:
LDD
#OC1_INT
;Store interrupt routine addresses
STD
$108,Z
;in the vector table (Note: this could
LDD
#OC4_INT
;be done in the file "init_int.asm".)
STD
$10E,Z
LDD
#OC5_INT
STD
$110,Z
LDD
#$0085
STD
GPTMCR
;set SUPV = 1, IARB = 5
LDD
#$0680
;GPT priority = 6, base vector = $80
STD
ICR
LDD
#$C800
;TCNT is Sys CLlk Div 4 (reset value)
STD
TMSK1
;each count = 238 nsec for 16.78 MHz Sys Clk
;enable interrupts for OC channels
WAI_FOR_INT
BRA
WAI_FOR_INT
;normally, this would go on to the next
;program task
* Each time that a match occurs between OC4 or OC5 and the Timer
* Counter (TCNT), the respective OC channel will toggle. If the software
* driver for the OC channel does not service an OC flag for some reason,
* a match will occur each 65,535 TCNT counts. OC1 is a special case. When
* it matches with TCNT, it will drive pins OC1-3 to the level written to
* the respective bits in the OC1D register.
* Following are the interrupt routines. In each one, a new future value
* is written into the appropriate TOC register.
OC5_INT:
;interrupt routine for OC5
LDD
TI4O5
ADDD
#$400
STD
TI4O5
;add #$400 to value in OC5 register
BCLRW
TFLG1 $8000
;clear I4O5 flag
RTI
OC4_INT:
;interrupt routine for OC4
LDD
TOC4
ADDD
#$200
STD
TOC4
;add #$200 to value in OC4 register
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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