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參數(shù)資料
| 型號： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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register. However, if this is done arbitrarily, there is a possibility that the QSPI will be active and will
be driving all of the chip selects low. Thus, the CPU could read bits [3:6] as zero instead of one and
end up writing back an erroneous value to PQSPAR. In this situation, all of the chip selects would drive
low all of the time. To avoid this scenario, only modify PORTQS when the QSPI is disabled (the SPE
bit is zero).
4.4.2.1 QSPI Initialization Example
This example illustrates how to initialize the QSPI in the wrap-around mode, with eight data bits per
transfer and active-low peripheral chip-select pins. Modifying the code to disable the wrap-around mode
is very simple. The modification is explained in the comments.
This example is in the file “qspiinit.asm” in the archive “16Z1_init” on the Freeware Data System.
INCLUDE
'EQUATES.ASM'
;file of register equates
INCLUDE
'INIT_RES.ASM'
;initialize reset vector
INCLUDE
'INIT_INT.ASM'
;initialize interrupt vectors
ORG
$200
;begin program at $200 after the exception table
INIT_SIM:
LDAB #$0F
;initialize K registers: YK,ZK to bank $F, XK to bank 0
TBEK
TBYK
TBZK
CLRB
TBXK
LDAA #$7F
STAA SYNCR
;increase clock speed
CLR SYPCR
;disable software watchdog
INIT_QSPI:
LDD SPCR1
ANDD #$7F
STD SPCR1
;Clear the SPE bit to disable the QSPI. Enabling the
;QSPI is the last step in the initialization sequence.
* The next commands read and clear the flags in SPSR. These flags are the
* QSPI finished flag (SPIF), the mode fault flag (MODF), and the halt
* acknowledge flag (HALTA). The SPIF bit is usually the flag of interest. It is
* set by the QSPI upon completion of a serial transfer when the address of the
* command being executed matches the ENDQP. If wrap-around mode is enabled, the
* SPIF bit is set each time the QSPI cycles through the queue. If interrupts
* are enabled, assertion of the SPIF bit causes an interrupt.
LDAB SPSR
ANDB #$00
STAB SPSR
;read and clear flags in SPSR
* The next command defines the initial states of the chip select signals in PORTQS
* (formerly called QPDR).
* The chip selects may be active high or active low. The initial state set in
* the PORTQS is the inactive state. The active state is selected in the command RAM
* In this example, the initial state of the chip
* select lines is high, and the initial state of SCK is low. This defines the
* chip selects to be active low and SCK to be active high. The SCI TXD signal
* bit is not affected.
LDAB #$7B
STAB PORTQS
;define initial states of chip selects/SCK
STAB PQSPAR
;Assign all pins to the QSPI. Pins can be
;assigned to the QSPI or for general
;purpose I/O on a pin by pin basis.
LDAB #$7E
STAB DDRQS
;Select the direction of the signal lines
;as outputs, except for MISO.
LDD #$8002
STD SPCR0
;Configure the QSPI as master, select
;8 data bits per transfer, set the inactive
;state of SCK as low, capture data on the
;leading edge of SCK, baud rate is 4.19 MHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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