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參數(shù)資料
| 型號(hào)： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
4.2.4 Periodic Interrupt Timer Register (PITR)
PITR and PICR control the periodic interrupt timer (PIT). The PIT begins to run when a timing modulus
is written to the PITM field in PITR. However, interrupt requests from the PIT are recognized only after
an interrupt priority level is written into the PIRQL field in the PICR. Clearing PITM stops the timer; clear-
ing PIRQL disables interrupts, but the timer continues to run. Because the CPU treats external inter-
rupts as SIM interrupt requests, PIT interrupts take precedence over external interrupts of the same
priority. To use the timer, proceed as follows.
1. Make certain that there is a vector to the interrupt service routine in the exception vector table,
and that there is a service routine at the address pointed to.
2. Select whether or not to prescale the timer clock signal (PTP bit in PITR).
3. Select the timing modulus or interrupt rate (PITM field in PITR).
4.2.5 Periodic Interrupt Control Register (PICR)
1. Determine the appropriate PIT vector number and interrupt priority.
2. Write vector number and interrupt priority to PIV and PIRQL fields in PICR.
4.2.6 Chip-Select Pin Assignment Registers (CSPAR0 and CSPAR1)
The chip-select pins can be used in a number of ways. CSPAR determine the functions of the pins.
1. Set up the chip-select pins for discrete output, 8-bit chip-select operation, 16-bit chip-select op-
eration, or alternate function.
2. If a chip-select circuit is used to generate an interrupt acknowledge signal, it must be configured
for chip-select operation. However, if a chip-select circuit is used to generate an autovector, the
pin can also be used for discrete output or its alternate function.
4.2.7 Chip-Select Base Address Registers (CSBARBT, CSBAR[0:10])
Chip-select signals are asserted when the CPU accesses certain ranges of addresses. The base ad-
dress registers specify the address ranges for each chip-select circuit.
1. Reprogram the base address and/or blocksize of CSBOOT if desired. The default value out of
reset is a base address of $000000 with a blocksize of 1 Mbyte.
2. Program the base address and block size for each chip-select circuit that is used. The base ad-
dress must be on a word boundary of the block size. For example, for an 8 Kbyte block size, the
base address can be $2000, $4000, $6000, $8000, etc. If a chip-select circuit is used to generate
an interrupt acknowledge signal or an autovector, the base address register must be set to
$FFF8 or higher because interrupt acknowledge cycles occur in CPU space. Remember that the
CPU16 cannot access memory locations $080000 to $F7FFFF, so do not program these ad-
dresses in the base address register.
4.2.8 Chip-Select Option Registers (CSORBT and CSOR[0:10])
The option registers control the conditions under which a chip-select signal is asserted.
1. Reprogram the options for CSBOOT if desired. Reducing the number of wait states from the re-
set value of 13 increases execution speed.
2. Program the option registers for each chip-select circuit used.
A. MODE — Select asynchronous mode (%0) unless using the ECLK output to provide synchro-
nous bus timing for 6800 peripherals. In synchronous mode (%1), the STRB and DSACK fields
have no effect.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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