參數(shù)資料
型號： MC68HC16Z1VEH16
廠商： Freescale Semiconductor
文件頁數(shù)： 24/56頁
文件大?。?/td> 0K
描述： IC MCU 16BIT 1K FLASH 132-PQFP
標準包裝： 36
系列： HC16
核心處理器： CPU16
芯體尺寸： 16-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
MC68HC16Z1TUT/D
the CPU, including topics such as the CPU16’s DSP instructions and how they can be applied in a real
system, the architectural differences between the M68HC11’s CPU and the CPU16, the CPU16 instruc-
tion set and the different addressing modes, the difference between program and data space, and the
CPU16’s internal registers.
Initial stack pointer, program counter, IZ register, and extension register values are fetched from boot
ROM. Other CPU resources that must be initialized include the exception vector table and the condition
code register. Also, the memory map must be allocated.
4.1.1 The CPU16 Memory Map and Bank Switching
The CPU16 memory map is divided into 16 pages. These pages are called banks. Each bank is 64
Kbytes long for a total of 1 Mbyte of available memory. If the memory is further divided into program and
data space, 2 Mbytes are available — 1 Mbyte for program space and 1 Mbyte for data space. However,
to accomplish this, the function code pins must be externally decoded.
4.1.1.1 The Memory Map
Assuming combined program and data space, the CPU16 can address 1 Mbyte of memory. Because
the MCU has 24 address lines, the memory map begins at address $000000 and ends at $FFFFFF.
However, when the CPU is driving the address bus, ADDR[23:20] follow the logic state of ADDR19. This
means that if the CPU drives ADDR19 high, then ADDR[23:20] will also be high. Likewise, if the CPU
drives ADDR19 low, then ADDR[23:20] will also be low. Thus, there is a large gap in the middle of the
memory map that the CPU cannot access. This gap begins at $080000 and ends at $F7FFFF. Table 5
illustrates examples of accessible and inaccessible memory.
The address line comparators used for matches between the address bus and the chip select base ad-
dress registers (CSBAR) in the system integration module (SIM) still do a comparison on all 24 address
lines. As address lines A[23:19] always have the same value, i.e., all high or all low, the address com-
parators will never find a match between a CSBAR and the physical address bus if a value between
$08000 and $F7FFFF is in the CSBARx register.
The memory map for combined program and data space is shown in Figure 17. As shown in Figure
17, the memory map is divided into 16 banks of memory, and each bank is 64 Kbytes long. The most
significant nibble of the addresses in banks 0 through 7 is $0, and the most significant nibble of the ad-
dresses in banks 8 through 15 is $F.
Table 5 Examples of Accessible and Inaccessible Addresses
Hex Address
A[23:20]
A[19:16]
A[15:12]
A[11:8]
A[7:4]
A[3:0]
Accessible?
$04000
%0000
0100
0000
yes
$08000
%0000
1000
0000
no
$F8000
%1111
1000
0000
yes
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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