參數(shù)資料
型號(hào): MC68HC16Z1VEH16
廠商: Freescale Semiconductor
文件頁數(shù): 10/56頁
文件大?。?/td> 0K
描述: IC MCU 16BIT 1K FLASH 132-PQFP
標(biāo)準(zhǔn)包裝: 36
系列: HC16
核心處理器: CPU16
芯體尺寸: 16-位
速度: 16MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 132-BQFP 緩沖式
包裝: 托盤
MC68HC16Z1TUT/D
Another way to control power supply noise created by the MCU is to put a small inductor in series with
the power supply lines for the port drivers. This method can help control noise on the power traces of
the PCB. However, it should be used only as a last resort, because it can introduce other noise prob-
lems. Also, a series inductor in the power supply line will probably have little effect on radiated noise,
which is generally a result of the port driver switching speed. Limiting instantaneous current change by
putting an inductor in series with the power supply pin for the port will not appreciably affect the current
through a particular driver because the integrated circuit generally has enough internal capacitance to
support an instantaneous current surge while the driver switches.
Figure 11 Proper Placement of a Bypass Capacitor
The VDDSYN and VSTBY supply pins should be separated and isolated from VDD with a low pass filter.
Any supply noise present on VDDSYN will translate into shifts in the system clock generated from the
PLL. Always supply power to VDDSYN, even when using an external oscillator and bypassing the internal
PLL.
2.8.2 Suggestions for Reducing Emissions
In general, follow standard design practices for EMC. A list of techniques that are often used in board
design follows.These techniques are guidelines for good design, not strict rules, and are not specific to
designs that incorporate the MC68HC16Z1.
Minimize the number of devices on the board. Capacitive coupling tends to occur around the holes
that connect a particular layer of the board to the power and ground planes.
Use a canned oscillator instead of a crystal, to reduce emissions from the oscillator. If a crystal circuit
must be used, locate it as centrally as possible.
Use a four layer PCB. As a general rule, a multilayer board is at least 10 times better than a two layer
board for both emissions and immunity. To reduce emissions even further, enclose the signal traces
between the power and ground planes because the added capacitance between the signal trace and
ground results in a lower characteristic impedance.
Plot thick layout lines with the layout program, then cut the actual traces on the board thin.
If a trace that conducts a high frequency signal must be routed on the surface of the PCB, route ground
traces parallel to it to reduce radiation and crosstalk. Connect the ground traces to ground planes at
varied intervals not to exceed the wavelength/4 at the highest frequency or harmonic expected.
Round off PCB trace corners as much as possible to reduce the amount of excess capacitance that
is introduced to the trace at corners.
Make spacing between adjacent active traces greater than the trace width to minimize crosstalk.
Put a chassis ground ring on the periphery of each layer of the PCB, to intercept the field coming off
the board. Interconnect these rings with small ceramic capacitors.
Use ferrite chokes when troubleshooting. Placing a choke around a signal line and the return conduc-
tor carrying a differential signal causes fields developed in the ferrite core by the opposing currents to
cancel. Ferrite chokes can also be used on input/output lines. Because board-mounted chokes in-
332TUT VDD LAYOUT
GND PLANE
POWER PLANE
BYPASS
CAP
VDD PIN
(.1
F TYPICAL)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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