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參數(shù)資料
| 型號(hào)： | MC68HC16Z1VEH16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT 1K FLASH 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | HC16 |
| 核心處理器： | CPU16 |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68HC16Z1TUT/D
2 Designing the Hardware
2.1 Using Data Bus Pins to Configure the MCU
The logic level of the data bus pins during reset determines many important operating characteristics
of the MCU. Ensuring that the data bus is in a known condition during reset is vital to proper operation
because the state of each data bus pin is sampled on the rising edge of the RESET signal. The data
bus pins have weak internal pull-up circuitry that should cause them to default to a logic one if left float-
ing (the pull-up current is 15 to 120
A). However, since it is possible for external bus loading to over-
come these internal pull-ups, it is a good idea to drive data bus pins that are critical to successful
operation of the application to a known condition during reset and for at least 5 ns afterwards (there is
a 5 ns hold time requirement after the release of RESET for a data bus pin to be recognized at a par-
ticular logic level). Table 1 shows how each data bus pin affects the system configuration.
As an example, Table 1 shows that the state of data bus pin 0 (DATA0) during reset determines whether
CSBOOT operates as a 16-bit chip-select or as an 8-bit chip-select. Likewise, data bus pin 1 (DATA1)
determines whether the CS0/BR, CS1/BG, and CS2/BGACK pins function as chip-select lines or as bus
control signals. After reset, software can make other selections for these pins by writing to the appro-
priate pin assignment register.
A simple method of pulling a data bus pin high is to connect a 10 K
resistor between it and the 5 volt
supply. Although putting a resistor on a data bus pin degrades performance at higher frequencies, many
designers use resistive pull-ups without significant side effects. The preferred method of driving data
bus pins during reset is by means of an active driver. A circuit to perform this function is shown in Figure
1. This circuit uses a 3-state buffer, such as a 74HC244 non-inverting octal driver, and meets the 5 ns
hold time requirement. While this method does require external circuitry, it is recommended when high
levels of noise may be encountered or when high reliability of operation is an overriding concern.
Tie 74HC244 inputs high or low, respectively, so that the desired logical values will be driven to the in-
dividual data bus pins when the output enable (OE) pin is driven low. The OE will be driven low when
the following three conditions are met: RESET is low, data strobe (DS) is high, and read/write (R/W) is
Notes:
1. Slave mode is not a supported mode; it is used for factory testing. The slave mode must not be used in a cus-
tomer application.
Table 1 Reset Mode Selection
Mode Select Pin
Default Function (Pin Left High)
Alternate Function (Pin Pulled Low)
DATA0
CSBOOT is 16-Bit Port
CSBOOT is 8-Bit Port
DATA1
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK0, DSACK1, AVEC, DS, AS, SIZE
PORTE I/0 pins
DATA9
IRQ[7:1], MODCLK
PORTF I/0 pins
DATA11
Slave Mode Disabled1
Slave Mode Enabled1
MODCLK
VCO = System Clock
EXTAL = System Clock
BKPT
Background Mode Disabled
Background Mode Enabled
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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