參數(shù)資料
型號： MC68HC16Z1VEH16
廠商： Freescale Semiconductor
文件頁數(shù)： 42/56頁
文件大?。?/td> 0K
描述： IC MCU 16BIT 1K FLASH 132-PQFP
標準包裝： 36
系列： HC16
核心處理器： CPU16
芯體尺寸： 16-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
4.6.1 ADC Initialization Example
This program initializes the ADC and samples the AD0 pin. It uses the single-channel four conversion
sequence. The most recent conversion will be in the E register, and its format will be right-justified un-
signed. Be sure to connect VDDA, VSSA, VRH, and VRL as described above in 4.6 Configuring the An-
alog-to-Digital Converter. Connect an input signal to the AD0 pin. Make sure that the input is within
the range of VRH and VRL.
This example is in the file “adc_init.asm” in the archive “16Z1_init” on the Freeware Data System.
INCLUDE
'EQUATES.ASM'
;register equates
INCLUDE
'INIT_RES.ASM' ;initialize reset vector
INCLUDE
'INIT_INT.ASM' ;initialize interrupt vectors
ORG
$200
CLRE
INIT_SIM:
LDAB
#$0F
;set K fields to $F to point to internal regs
TBEK
LDAA
#$7F
STAA
SYNCR
;increase clock speed
CLR
SYPCR
;disable software watchdog
INIT_ADC:
LDD
#$0000
STD
ADCMCR
;enable ADC
LDD
#$0043
;STS field = 8 A/D clocks
STD
ADCTL0
;8-bit, sample period=SYS CLOCK/8
START_ADC:
LDD
#$0000
STD
ADCTL1
;single 4 conversion, single channel, AD0
;writing to the ADCTL1 reg starts conversion
LDAA
#$80
SEE_IF_DONE:
BITA
ADSTAT
;check for the Sequence Complete Flag
BEQ
SEE_IF_DONE
;wait until conversion is complete
LDE
RJURR0
;read result in lower byte of register
BRA
START_ADC
;go get another sample
INT
RTI
;unused interrupts point here
5 Troubleshooting
Because of the complexity of the MCU, there are a considerable number of potential ‘fatal flaws’ that
can cause a prototype application to either not operate from power up or to fail soon after. This section
covers common problems, causes, and fixes. This is not an exhaustive discussion, but it is intended to
be used as a check list of the main problem areas that can cause an application to fail.
5.1 Critical Signals to Check
RESET should stay low for at least 512 clocks during a power-on reset. If using the internal PLL, RE-
SET will remain low for a little longer because the VCO must lock first. RESET should then go high
and remain high.
CLKOUT should be at the system clock frequency. If MODLCK is held high at the release of reset,
CLKOUT should be 512 times the frequency going into EXTAL (8.389 MHz for a 32.768 kHz crystal).
Make sure that the frequency is exact, as a measurable error may indicate limp mode and oscillator
faults. If MODCLK is held low at the release of reset, the frequency on CLKOUT should be the fre-
quency going into EXTAL.
Immediately after reset, CSBOOT should pulse low five times for a 16-bit port and nine times for an 8-
bit port.
FREEZE should be low and HALT should be high. Otherwise, the MCU is halted, or is in BDM.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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