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參數(shù)資料
| 型號： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機適配器 |
| 文件頁數(shù)： | 86/128頁 |
| 文件大?。?/td> | 1591K |
| 代理商： | CL-PD6722 |
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PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
86
DMA OPERATION (CL-PD6722 only)
14.4.2
Configuring the Socket Interface for I/O
For DMA support, bit 5 of the
Interrupt and General Control
register must be set to ‘1’ to put the card
interface in I/O Card Interface mode.
14.4.3
Preventing Dual Interpretation of DMA Handshake Signals
If the WP/-IOIS16 pin is being used as the DMA request line, the following should be considered:
1)
Bit 4 of the
Interface Status
register is now the level of the DMA request line from the card.
2)
Bit 5 of the socket’s two I/O Window Control registers should be set to ‘0’.
If a socket’s BVD2/-SPKR pin is being used as the DMA request line, speaker or LED output from that
socket is not available.
If -INPACK is selected as the DMA request input, then bit 7 of the
Misc Control 1
register should be set
to ‘0’ to disable use of this signal as input acknowledge control.
No other register bits require special settings to accommodate DMA support on a socket interface.
14.4.4
Turning On DMA System
The DMA System bit (bit 6 of the
Misc Control 2
register) should be programmed to ‘1’ to allow DMA
operation and to redefine ISA bus interface pins for DMA support as in
Figure 14-1
.
14.5 The DMA Transfer Process
As soon as the selected DMA request input from the card becomes active (low) and the FIFO empties,
IRQ10 becomes active (high), signifying a DMA request to the system. The system then responds with
an active (low) -DACK at IRQ9, which enables the CL-PD6722 to decode any ISA bus DMA transfers that
may occur and perform the corresponding transfers at the card. Normal card I/O or memory reads or
writes may be interspersed with DMA read and write cycles.
14.6 Terminal Count to Card at Conclusion of Transfer
At the conclusion of each transfer process, systems send active (high) TC (terminal count) pulses to the
-VPP_VALID pin during the last DMA cycles to the CL-PD6722.
For a DMA write cycle, TC active is signaled at the socket interface as the -OE pin going low during DMA-
type read cycles from the PC Card.
For a DMA read cycle, TC active is signaled as the -WE pin going low during DMA-type write cycles to
the PC Card.
相關PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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