參數(shù)資料
型號: CL-PD6722
廠商: Cirrus Logic, Inc.
英文描述: ISA-TOOPC-CARD HOST ADAPTERS
中文描述: ISA的TOOPC卡主機(jī)適配器
文件頁數(shù): 74/128頁
文件大?。?/td> 1591K
代理商: CL-PD6722
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
74
TIMING REGISTERS
10.3 Recovery Timing 0–1
There are two separate Recover Timing registers, each with identical fields. These registers are located
at the following indexes:
Index
3Ch
3Fh
Recovery Timing
Recovery Timing 0
Recovery Timing 1
The Recovery Timing register for each timing set controls how long a PC Card cycle’s command (that is,
-OE, -WE, -IORD, -IOWR; see
page 16
) recovery will be, in terms of the number of internal clock cycles.
The overall command recovery timing length Ris programmed by selecting a 2-bit prescaling value (bits
7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits
5:0) to which that prescalar is multiplied to produce the overall command recovery timing length according
to the following formula:
R
= (
N
pres
×
N
val
) + 1
Equation 10-3
The value of R representing the number of internal clock cycles for command recovery, is then multiplied
by the internal clock’s period to determine the command recovery time (see
Section 15.3.6
for further dis-
cussion).
Bits 5:0 — Recovery Multiplier Value
This field indicates an integer value N
val
from 0 to 63; it is combined with a prescalar value (bits
7:6) to control the length of recovery time after a command is active.
Bits 7:6 — Recovery Prescalar Select
This field chooses one of four prescalar values N
pres
that are combined with the value of the Re-
covery Multiplier Value (bits 5:0) to control the length of recovery time after a command is active.
Register Name:
Recovery Timing 0–1
Index:
3Ch, 3Fh
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Recovery Prescalar Select
Recovery Multiplier Value
RW:00
RW:000011
00
01
10
11
N
pres
= 1
N
pres
= 16
N
pres
= 256
N
pres
= 8192
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