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| 型號(hào)： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機(jī)適配器 |
| 文件頁(yè)數(shù)： | 50/128頁(yè) |
| 文件大?。?/td> | 1591K |
| 代理商： | CL-PD6722 |
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PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
50
I/O WINDOW MAPPING REGISTERS
Bit 7 — Timing Register Select 1
This bit determines the access timing specification for I/O Window 1 (see
page 72
).
7.2
System I/O Map 0–1 Start Address Low
There are two separate System I/O Map Start Address Low registers, each with identical fields. These
registers are located at the following indexes:
Index
8h
Ch
System I/O Map Start Address Low
System I/O Map 0 Start Address Low
System I/O Map 1 Start Address Low
Bits 7:0 — Start Address 7:0
This register contains the least-significant byte of the address that specifies the beginning of the
I/O space within the corresponding I/O map. I/O accesses that are equal or above this address
and equal or below the corresponding System I/O Map End Address will be mapped into the I/O
space of the corresponding PC Card.
The most-significant byte is located in the
System I/O Map 0–1 Start Address High
register (see
page
50
).
7.3
System I/O Map 0–1 Start Address High
There are two separate System I/O Map Start Address High registers, each with identical fields. These
registers are located at the following indexes:
Index
9h
Dh
System I/O Map Start Address High
System I/O Map 0 Start Address High
System I/O Map 1 Start Address High
Bits 15:8 — Start Address 15:8
This register contains the most-significant byte of the Start Address. See the description of the Start
Address field associated with bits 7:0 of the
System I/O Map 0–1 Start Address Low
register.
0
1
Accesses made with timing specified in Timing Set 0.
Accesses made with timing specified in Timing Set 1.
Register Name:
System I/O Map 0–1 Start Address Low
Index:
08h, 0Ch
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Start Address 7:0
RW:00000000
Register Name:
System I/O Map 0–1 Start Address High
Index:
09h, 0Dh
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Start Address 15:8
RW:00000000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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