參數(shù)資料
型號： CL-PD6722
廠商： Cirrus Logic, Inc.
英文描述： ISA-TOOPC-CARD HOST ADAPTERS
中文描述： ISA的TOOPC卡主機適配器
文件頁數(shù)： 105/128頁
文件大小： 1591K
代理商： CL-PD6722
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
105
PRELIMINARY DATA SHEET v3.1
ELECTRICAL SPECIFICATIONS
Table 15-17. DMA Read Cycle Timing (CL-PD6722 only)
Symbol
Parameter
MIN
MAX
Units
t
1
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
t
2
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active
1
(S
×
Tcp) – 10
ns
t
3
Command: -IOWR pulse width
2
(C
×
Tcp) – 10
ns
t
4
Recovery: -IOWR inactive to end of cycle
3
(R
×
Tcp) – 10
ns
t
5
-WAIT active from -IOWR active
(C – 2)Tcp – 10
ns
t
6
-WAIT inactive to -IOWR inactive
2 Tcp
ns
t
7
System TC (-VPP_VALID high) to -IOWR
40
ns
t
8
-IOWR to begin of card TC (-WE)
4
25
50
ns
t
9
End of card TC (-WE) to -IOWR inactive
4
25
50
ns
1
The Setup time is determined by the value programmed into the
Setup Timing
register, index 3Ah/3Dh. Using the Timer
Set 0 default value of 01h, the setup time would be 70 ns. S = (N
pres
×
N
val
+ 1), see page
98
.
2
The Command time is determined by the value programmed into the
Command Timing
register, index 3Bh/3Eh. Using
the Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N
pres
×
N
val
+ 1), see page
98
.
3
The Recovery time is determined by the value programmed into the
Recovery Timing
register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
pres
×
N
val
+ 1), see page
98
.
4
Based on an internal clock period of 40 ns (25 MHz).
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