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| 型號(hào)： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機(jī)適配器 |
| 文件頁數(shù)： | 77/128頁 |
| 文件大小： | 1591K |
| 代理商： | CL-PD6722 |
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CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
77
PRELIMINARY DATA SHEET v3.1
USING GPSTB PINS FOR EXTERNAL PORT CONTROL
(CL-PD6722 only)
12. USING GPSTB PINS FOR EXTERNAL PORT CONTROL
(CL-PD6722 only)
The CL-PD6722 provides pins that can be programmed to function as general-purpose strobes to exter-
nal latches or buffers, allowing them to serve as read ports or write ports mapped into the CL-PD6722
register set.
Configuring a GPSTB pin as a read port allows an easy way to read additional card status such as VS1#
and VS2# levels, a card socket microswitch status, a card port cover microswitch status, card eject sole-
noid position status, or general system signal status.
Configuring a GPSTB pin as a write port allows an easy way to control additional features such as card-
state LEDs, card mechanism solenoids, or motor eject mechanisms.
12.1 Control of GPSTB Pins
The
Extension Control 2
register controls the GPSTB pins.
For the CL-PD6722, the A_GPSTB pin is controlled by the
Extension Control 2
register at Socket A
(index 2Fh, extended index 0Bh), and the B_GPSTB pin is controlled by the
Extension Control 2
register
at Socket B (index 6Fh, extended index 0Bh).
The following table summarizes how the GPSTB pins are configured and how data is accessed from
external ports created by using a GPSTB pin to control an external read or write port.
Programming the Extension Control 2 Register
There is one
Extension Control 2
register per GPSTB pin. Each register has identical GPSTB control
bits, as follows. See also the description of this register in Section 9.7.6.
Bit 5 allows programming of the active level of GPSTB, with the default being active-low. Setting bit 5 to
‘1’ causes a GPSTB output to be low normally and high (active) upon external data access.
Table 12-1. Registers for Control and Data of GPSTB Pins
Pin Name
GPSTB Control Access
External Port Data Access
A_GPSTB (CL-PD6722)
Set register 2E to 0Bh,
access
Extension Control 2
register at 2F
Set register 2E to 0Ah,
access
External Data
register at 2F
B_GPSTB (CL-PD6722)
Set register 6E to 0Bh,
access
Extension Control 2
register at 6F
Set register 6E to 0Ah,
access
External Data
register at 6F
Register Name:
Extension Control 2
Index:
2Fh and 6Fh
Bit
7
Extended Index:
0Bh
Bit
4
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
6
Bit
5
Bit
3
Bit
2
Bit
0
Reserved
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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