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參數(shù)資料
| 型號： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機適配器 |
| 文件頁數(shù)： | 15/128頁 |
| 文件大小： | 1591K |
| 代理商： | CL-PD6722 |
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CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
15
PRELIMINARY DATA SHEET v3.1
PIN INFORMATION
SPKR_OUT*/
C_SEL
Speaker Out / Chip Select
: This I/O pin can
be used as a digital output to a speaker to
allow a system to support a PC Card’s -SPKR
pin for fax/modem/voice and audio. During
reset this pin also serves as a chip-configura-
tion input.
If the level on this pin is low when PWRGOOD
rises, the CL-PD6710 is configured to support
cards as a PC Card Socket 2 device, and the
CL-PD6722 is configured to support cards as
PC Card Socket 2 and Socket 3 devices.
If the level on this pin is high when PWRGOOD
rises, the CL-PD6710 is configured to support
cards as a PC Card Socket 0 device, and the
CL-PD6722 is configured to support cards as
PC Card Socket 0 and Socket 1 devices.
This pin is internally pulled up during reset so
that default configuration of the chip as a
Socket 0 (and Socket 1 for CL-PD6722) is
facilitated. Adhere to the minimum pulse-width
timing specification for PWRGOOD to allow
the internal pull-up to operate and ensure the
default configuration. Refer to the Socket Index
field on page
33
for more information on chip
configuration.
After reset operations have completed, this pin
defaults to high-impedance, and can then be
enabled as a totem-pole speaker output by the
setting of a card socket’s Speaker Enable bit
(
Misc Control 1
register, bit 4). This output
then becomes the negative polarity XOR of
each socket’s BVD2/-SPKR/-LED input that
has its Speaker Enable bit set. For a descrip-
tion of socket index values, refer to
Section
5.1
.
142
202
1
I/O-
PU
4
12
mA
CLK
Clock:
This input is connected to the ISA bus
OSC signal. A 14.318-MHz signal is used to
derive the internal 25-MHz clock used for all
socket timing. Alternately, a 25-MHz clock
source can be directly connected and the inter-
nal synthesizer bypassed.
102
163
1
I
4
–
-VPP_VALID
In default mode this is a status input that can
be used by software as an indication that the
V
PP
power supply is stable.
When the CL-PD6722 is in DMA mode (see
Misc Control 2, bit 6), this input is connected to
the TC (Terminal Count) signal of the ISA bus.
In DMA mode, this signal is active-high.
4
3
1
I
1
–
ISA_VCC
System Bus V
CC
:
This supply pin can be set
to 3.3 or 5.0 V. The ISA Bus Interface pin group
(this table) operates at the voltage applied to
this pin independent of the voltage applied to
other pin groups.
76, 135
138, 195
2
PWR
–
–
Table 2-1.
ISA Bus Interface Pins
(cont.)
Pin Name
Description
Pin Number
Qty.
I/O
Pwr. Drive
CL-PD6710
CL-PD6722
相關PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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