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參數(shù)資料
| 型號： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機適配器 |
| 文件頁數(shù)： | 83/128頁 |
| 文件大?。?/td> | 1591K |
| 代理商： | CL-PD6722 |
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CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
83
PRELIMINARY DATA SHEET v3.1
DMA OPERATION (CL-PD6722 only)
14. DMA OPERATION (CL-PD6722 only)
14.1 DMA Capabilities of the CL-PD6722
The CL-PD6722 include support of a DMA-capable PC Card slave and the movement of DMA data
to/from the card with the ISA bus as a DMA master.
Only one socket at a time should be enabled for DMA transfer because the ISA bus DMA handshake sig-
nals are shared between both socket interfaces.
DMA transfers to and from the DMA-capable PC Card may be 8- or 16-bit, as indicated by the size of the
ISA bus DMA cycle.
1
14.2 DMA-Type PC Card Cycles
Transfer of DMA data to or from a card is achieved through use of a special DMA-type PC Card interface
cycle. This cycle is defined to not conflict with standard PC Card memory or I/O cycles.
A card that is DMA-capable can distinguish PC Card interface cycle types presented by the CL-PD6722
according to the following table:
NOTE:
Bits 7 and 6 of the
Extension Control 1
register must be nonzero for
Table 14-1
to be true; otherwise only
standard PC Card cycles will be issued to the card.
The PC Card address is also undefined during the DMA read or write cycle.
Card DMA data read and write cycles transfer DMA data to or from a DMA-capable PC Card. These
cycles are distinguished from normal card I/O cycles by the -REG signal being high during the cycle,
which is an undefined condition in the PC Card Standard.
1
Transfer size at socket interface is the same as transfer size on an ISA bus. For 8-bit DMA transfers, connect CL-PD6722
DMA handshake signals to ISA bus DMA channels 0, 1, 2, or 3. For 16-bit transfers, connect CL-PD6722 DMA handshake
signals to ISA bus DMA channels 5, 6, or 7.
Table 14-1. Four Card Cycle Types for DMA-Type PC Card Interface
Socket Interface Cycle Type
Function of -WE/-OE
Function of
-IORD/-IOWR
Function of -REG
Card Memory Read/Write
Data transfer signaling
Always inactive high
Always inactive high
Attribute Memory Read/Write
Data transfer signaling
Always inactive high
Always low
Card I/O Read/Write
Always inactive high
Data transfer signaling
Low = non-DMA I/O cycle
Card DMA Data Read/Write
Terminal count outputs
Data transfer signaling
High = DMA cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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