參數(shù)資料
型號: CL-PD6722
廠商: Cirrus Logic, Inc.
英文描述: ISA-TOOPC-CARD HOST ADAPTERS
中文描述: ISA的TOOPC卡主機(jī)適配器
文件頁數(shù): 56/128頁
文件大?。?/td> 1591K
代理商: CL-PD6722
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
56
MEMORY WINDOW MAPPING REGISTERS
8.5
Card Memory Map 0–4 Offset Address Low
There are five separate Card Memory Map Offset Address Low registers, each with identical fields. These
registers are located at the following indexes:
Index
14h
1Ch
24h
2Ch
34h
Card Memory Map Offset Address Low
Card Memory Map 0 Offset Address Low
Card Memory Map 1 Offset Address Low
Card Memory Map 2 Offset Address Low
Card Memory Map 3 Offset Address Low
Card Memory Map 4 Offset Address Low
Bits 7:0 — Offset Address 19:12
This register contains the least-significant byte of the quantity that will be added to the host
memory address, which will determine where the memory access will occur in the PC Card
memory map.
The most-significant six bits are located in the
Card Memory Map 0–4 Offset Address High
register (see page
56
).
8.6
Card Memory Map 0–4 Offset Address High
There are five separate Card Memory Map Offset Address High registers, each with identical fields. These
registers are located at the following indexes:
Index
15h
1Dh
25h
2Dh
35h
Card Memory Map Offset Address High
Card Memory Map 0 Offset Address High
Card Memory Map 1 Offset Address High
Card Memory Map 2 Offset Address High
Card Memory Map 3 Offset Address High
Card Memory Map 4 Offset Address High
Register Name:
Card Memory Map 0–4 Offset Address Low
Index:
14h, 1Ch, 24h, 2Ch, 34h
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Offset Address 19:12
RW:00000000
Register Name:
Card Memory Map 0–4 Offset Address High
Index:
15h, 1Dh, 25h, 2Dh, 35h
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Write Protect
REG Setting
Offset Address 25:20
RW:0
RW:0
RW:000000
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
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