參數(shù)資料
型號： CL-PD6722
廠商： Cirrus Logic, Inc.
英文描述： ISA-TOOPC-CARD HOST ADAPTERS
中文描述： ISA的TOOPC卡主機適配器
文件頁數(shù)： 78/128頁
文件大?。?/td> 1591K
代理商： CL-PD6722
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
78
USING GPSTB PINS FOR EXTERNAL PORT CONTROL
(CL-PD6722 only)
Bit 4 controls use of the respective GPSTB pin as a write strobe for an external general-purpose latch.
When the respective extended index is set to 0Ah and the index register is set to the respective 2Fh or
6Fh setting, I/O writes that access address 3E1h will result in the respective GPSTB signal being driven
active for the duration of the ISA bus IOW* signal being driven low.
Bit 3 controls use of the respective GPSTB pin a read strobe for an external general-purpose buffer. When
the respective extended index is set to 0Ah and the index register is set to the respective 2Fh or 6Fh set-
ting, I/O reads that access address 3E1h will result in the respective GPSTB signal being driven active
for the duration of the ISA bus IOR* signal being driven low.
Bit 2 cause the GPSTB output to be totem-pole instead of the default open-collector configuration. When
GPSTB outputs are totem-pole, their ‘high’ level is driven to the voltage of the ‘+5V’ pin, instead of to high-
impedance.
If neither bit 3 nor bit 4 is set, the respective GPSTB pin functions as a reserved input in a CL-PD6722
that is an internal pull-up to the ‘+5V’ pin. This internal pull-up is turned off whenever the GPSTB pin is
configured as a general-purpose strobe, or when the respective socket’s Pull-up Control bit is set to ‘1’.
Bits 7:6 and 1:0 are reserved and must be programmed to ‘0’. These bits should not be used as scratch-
pad bits.
External Data Port Access through the External Data Register
Data to be accessed from an external read or write port is mapped to the respective
External Data
reg-
ister at Extended Index 0Ah. This allows external data to be accessed as if it were a register in the
CL-PD67XX register set.
To achieve this mapping, the external data port’s buffer or latch data connections should be made to
SD[15:8] of the system bus for 16-bit systems, and to SD[7:0] of the system bus for 8-bit systems.
To support readback of data written to an external I/O port by use of a GPSTB pin, a shadow of the exter-
nal data register exists, which is read when an I/O read is done from the external data register location
corresponding to a GPSTB pin programmed as a write strobe.
For more information on the Socket A and Socket B versions of this register, see the description of this
register in Section 9.7.4 and Section 9.7.5.
Register Name:
External Data
Index:
2Fh
Bit
7
Extended Index:
0Ah
Bit
4
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
6
Bit
5
Bit
3
Bit
2
Bit
0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
相關PDF資料
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相關代理商/技術參數(shù)
參數(shù)描述
CL-PD6722-VC-B 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT
CL-PD6729-QC-C 制造商:BASIS 功能描述:
CLPD6729QCE 制造商:BASIS 功能描述:
CL-PD6729-QC-E 制造商:CIRRUS LOGIC 功能描述:
CL-PD6730-QC-B79030-648AC 制造商:CL 功能描述:CL-PD6730-QC-B79030-
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