參數(shù)資料
型號: CL-PD6722
廠商: Cirrus Logic, Inc.
英文描述: ISA-TOOPC-CARD HOST ADAPTERS
中文描述: ISA的TOOPC卡主機適配器
文件頁數(shù): 102/128頁
文件大?。?/td> 1591K
代理商: CL-PD6722
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
102
ELECTRICAL SPECIFICATIONS
Figure 15-8. PC Card Read/Write Timing When System Is 8-Bit
(SBHE Tied High)
Table 15-14. PC Card Read/Write Timing when System Is 8-Bit
Symbol
Parameter
MIN
MAX
Units
t
1
-REG or Address setup to Command active
1
(S
×
Tcp) – 10
ns
t
2
Command pulse width
2
(C
×
Tcp) – 10
ns
t
3
Address hold from Command inactive
3
(R
×
Tcp) – 10
ns
t
4
Data setup before Command inactive
(2 Tcp) + 10
ns
t
5
Data hold after command inactive
0
ns
1
The Setup time is determined by the value programmed into the
Setup Timing
register, index 3Ah/3Dh. Using the Timer
Set 0 default value of 01h, the setup time would be 70 ns. S = (N
pres
×
N
val
+ 1), see page
98
.
2
The Command time is determined by the value programmed into the
Command Timing
register, index 3Bh/3Eh. Using
the Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N
pres
×
N
val
+ 1), see page
98
.
3
The Recovery time is determined by the value programmed into the
Recovery Timing
register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
pres
×
N
val
+ 1), see page
98
.
-IOWR, -IORD,
t
1
t
2
t
3
-CE1
-REG,
A[25:0]
D[7:0]
Odd/even Data
D[15:8]
Read or
Write Cycle
XX
-OE, -WE
D[7:0]
Read Cycle
t
5
t
4
Write Cycle
Odd/Even Data
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