
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
35
PRELIMINARY DATA SHEET v3.1
OPERATION REGISTERS
a
Socket B is available on the dual-socket CL-PD6722.
b
This register affects both sockets (it is not specific to either socket).
c
These registers are not available on the CL-PD6710.
ATA Control
26h
66h
Chapter 9:
Extension
–
64
Scratchpad
System Memory Map 3 Start Address Low
System Memory Map 3 Start Address High
System Memory Map 3 End Address Low
System Memory Map 3 End Address High
Card Memory Map 3 Offset Address Low
Card Memory Map 3 Offset Address High
Extended Index:
c
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
Extended index 00h
Extended index 01h
Extended index 02h
Extended index 03h
Extended index 04h
Extended index 05h–09h
Extended index 0Ah
Extended index 0Bh
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
–
Chapter 8:
Memory Window
Mapping
53
54
54
55
56
56
65
–
65
66
66
67
–
69
71
Scratchpad
Data Mask 0
Data Mask 1
Extension Control 1 (formerly DMA
Control)
Maximum DMA Acknowledge Delay
Reserved
External Data
Extension Control 2
Extended Data
System Memory Map 4 Start Address Low
System Memory Map 4 Start Address High
System Memory Map 4 End Address Low
System Memory Map 4 End Address High
Card Memory Map 4 Offset Address Low
Card Memory Map 4 Offset Address High
Card I/O Map 0 Offset Address Low
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address Low
Card I/O Map 1 Offset Address High
Setup Timing 0
Command Timing 0
Recovery Timing 0
Setup Timing 1
Command Timing 1
Recovery Timing 1
Chapter 9:
Extension
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
65
53
54
54
55
56
56
52
52
52
52
72
73
74
72
73
74
Chapter 8:
Memory Window
Mapping
Chapter 7:
I/O Window
Mapping
Chapter 10:
Timing
Table 5-1.
Index Registers
(cont.)
Register Name
Index Value
Socket A
Chapter
Page
Number
Socket B
a