參數(shù)資料
型號(hào)： CL-PD6722
廠商： Cirrus Logic, Inc.
英文描述： ISA-TOOPC-CARD HOST ADAPTERS
中文描述： ISA的TOOPC卡主機(jī)適配器
文件頁數(shù)： 51/128頁
文件大?。?/td> 1591K
代理商： CL-PD6722
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
51
PRELIMINARY DATA SHEET v3.1
I/O WINDOW MAPPING REGISTERS
7.4
System I/O Map 0–1 End Address Low
There are two separate System I/O Map End Address Low registers, each with identical fields. These reg-
isters are located at the following indexes:
Index
Ah
Eh
System I/O Map End Address Low
System I/O Map 0 End Address Low
System I/O Map 1 End Address Low
Bits 7:0 — End Address 7:0
This register contains the least-significant byte of the address that specifies the termination of the
I/O space within the corresponding I/O map. I/O accesses that are equal or below this address
and equal or above the corresponding System I/O Map Start Address will be mapped into the I/O
space of the corresponding PC Card.
The most-significant byte is located in the
System I/O Map 0–1 End Address High
register (see
page
51
).
7.5
System I/O Map 0–1 End Address High
There are two separate System I/O Map End Address High registers, each with identical fields. These
registers are located at the following indexes:
Index
Bh
Fh
System I/O Map End Address High
System I/O Map 0 End Address High
System I/O Map 1 End Address High
Bits 15:8 — End Address 15:8
This register contains the most-significant byte of the End Address. See the description of the End
Address field associated with bits 7:0 of the
System I/O Map 0–1 End Address Low
register (see
page
51
).
Register Name:
System I/O Map 0–1 End Address Low
Index:
0Ah, 0Eh
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
End Address 7:0
RW:00000000
Register Name:
System I/O Map 0–1 End Address High
Index:
0Bh, 0Fh
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
End Address 15:8
RW:00000000
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相關(guān)代理商/技術(shù)參數(shù)
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CL-PD6729-QC-E 制造商:CIRRUS LOGIC 功能描述:
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