參數(shù)資料
型號： CL-PD6722
廠商： Cirrus Logic, Inc.
英文描述： ISA-TOOPC-CARD HOST ADAPTERS
中文描述： ISA的TOOPC卡主機適配器
文件頁數(shù)： 52/128頁
文件大小： 1591K
代理商： CL-PD6722
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
52
I/O WINDOW MAPPING REGISTERS
7.6
Card I/O Map 0–1 Offset Address Low
There are two separate Card I/O Map Offset Address Low registers, each with identical fields. These reg-
isters are located at the following indexes:
Index
36h
38h
Card I/O Map Offset Address Low
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the
Card I/O Map 0–1 Offset Address High
register (see
page
52
).
7.7
Card I/O Map 0–1 Offset Address High
There are two separate Card I/O Map Offset Address High registers, each with identical fields. These reg-
isters are located at the following indexes:
Index
37h
39h
Card I/O Map Offset Address High
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Bits 15:8 — Offset Address 15:8
This register contains the most-significant byte of the Offset Address. See the description of the
End Address field associated with bits 7:1 of the
Card I/O Map 0–1 Offset Address Low
register
(see page
52
).
a
This bit must be programmed to ‘0’.
Register Name:
Card I/O Map 0–1 Offset Address Low
Index:
36h, 38h
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Offset Address 7:1
0
a
RW:0000000
RW:0
Register Name:
Card I/O Map 0–1 Offset Address High
Index:
37h, 39h
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Offset Address 15:8
RW:00000000
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