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| 型號(hào)： | CL-PD6722 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | ISA的TOOPC卡主機(jī)適配器 |
| 文件頁(yè)數(shù)： | 61/128頁(yè) |
| 文件大小： | 1591K |
| 代理商： | CL-PD6722 |
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CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
61
PRELIMINARY DATA SHEET v3.1
EXTENSION REGISTERS
9.3
Misc Control 2
Bit 0 — Bypass Frequency Synthesizer
This bit determines internal time base.
Bit 1 — Low-Power Dynamic Mode
This bit determines whether Low-Power Dynamic mode is enabled. For maximum operational
power savings, keep this bit set to ‘1’.
Bit 2 — Suspend
This bit enables Suspend mode. After entering Suspend, AEN should be pulled high for lowest
power consumption. When this bit is high and AEN is high, all ISA bus interface inputs are turned
off. In 82386SL systems when the processor is in Suspend mode, the ISA bus interface signals
float; this feature will prevent high current flow in the CL-PD67XX inputs.
Bit 3 — 5V Core
This bit selects input threshold circuits for use when 3.3 or 5.0 volts is connected to the
CL-PD67XX CORE_VDD pins. This bit must be set to ‘0’ when the CORE_VDD pins are connect-
ed to 3.3 volts to preserve TTL-compatible input thresholds to the card socket.
Bit 4 — Drive LED Enable
NOTE:
This bit should be set to ‘0’ if in Memory Card Interface mode.
This bit determines whether -SPKR is used to drive an LED on the IRQ12 (see
page 14
) for disk
drives.
Register Name:
Misc Control 2
Index:
1Eh
Bit
7
Register Per: chip
Register Compatibility Type: ext.
Bit
1
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
IRQ15 Is RI
Out
DMA System
(CL-PD6722)
Three-State
Bit 7
Drive LED
Enable
5V Core
Suspend
Low-Power
Dynamic
Mode
RW:1
Bypass
Frequency
Synthesizer
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
0
1
Normal operation, internal clock = CLK input frequency x 7/4.
Internal clock = CLK input frequency (see
page 15
).
0
1
Clock runs always.
Normal operation, stop clock when possible.
0
1
Normal operation.
Stop Frequency Synthesizer, enable all Low-Power modes and disable socket access.
0
1
Normal operation: use when CORE_VDD pin is connected to 3.3 volts.
Selects input thresholds for use when 5.0 volts is connected to the CL-PD67XX CORE_VDD pins.
0
1
IRQ12 operates normally.
IRQ12 becomes an open-drain output suitable for driving an LED (driven whenever the card -SPKR
output is turned on, and the corresponding Speaker Is LED input bit (see page
64
) is set).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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