
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
71
PRELIMINARY DATA SHEET v3.1
EXTENSION REGISTERS
9.7.6
Extension Control 2
(CL-PD6722 only)
Bit 5 — Active-high GPSTB
Bit 4 — GPSTB on IOW*
(CL-PD6722 only)
Note that setting this bit forces the pull-ups on A_GPSTB (CL-PD6722) to be off, independent of
the setting of the Pull-Up Control bit (index 2Fh, extended index 03h, bit 5). See
Section 9.7.5
,
Chapter 12
, and
Chapter 13
.
Bit 3 — GPSTB on IOR*
(CL-PD6722 only)
Note that setting this bit forces the pull-ups on B_GPSTB (CL-PD6722) to be off, independent of
the setting of the Pull-Up Control bit (index 6Fh, extended index 03h, bit 5). See
Section 9.7.5
,
Chapter 12
, and
Chapter 13
.
Bit 2 — Totem-pole GPSTB
When GPSTB outputs are totem-pole, their ‘high’ level is driven to the level of the +5V pin, instead
of high-impedance.
Register Name:
Extension Control 2
Index:
2Fh
Bit
7
Extended Index:
0Bh
Bit
4
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
6
Bit
5
Bit
3
Bit
2
Bit
0
Reserved
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
0
1
GPSTB ouputs are active-low.
GPSTB ouputs are active-high.
0
1
A_GPSTB (CL-PD6722) pins are used as voltage sense.
A_GPSTB (CL-PD6722) pins are used to strobe I/O writes on SD[15:8].
0
1
B_GPSTB (CL-PD6722) pins (socket B) are used as voltage sense.
B_GPSTB (CL-PD6722) pins are used to strobe I/O reads on SD[15:8].
0
1
GPSTB ouputs are open-collector.
GPSTB ouputs are totem-pole.