
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
84
DMA OPERATION (CL-PD6722 only)
14.3 ISA Bus DMA Handshake Signal
A DMA request from the card is passed to the ISA bus as long as the socket interface FIFO is empty.
IRQ10 is used as the DMA request output to the ISA bus when bit 2 of the
Misc Control 2
register is ‘1’.
When bit 2 of the
Misc Control 2
register is ‘1’, IRQ9 is redefined as the active-low DMA acknowledge
input from the ISA bus. This signal must remain active for all DMA transfers through the CL-PD6722.
Figure 14-1. DMA Handshake Connections to the ISA Bus
to Make the CL-PD6722 DMA-Capable
Terminal counts are passed through to the card from the CL-PD6722 -VPP_VALID pin when bit 6 of the
Misc Control 2
register is ‘1’. For a DMA write process, the last-cycle terminal count condition is indicated
by -OE being active-low during a card DMA data read cycle. For a DMA read process, terminal count is
indicated by -WE being active-low during the last card cycle.
14.4 Configuring the CL-PD6722 Registers for a DMA Transfer
Program the registers as follows to configure a CL-PD6722 socket interface for DMA transfer to/from a
DMA-capable PC Card:
1.
Select which pin on the PC Card interface will serve as the DMA request input.
2.
Configure the socket interface as I/O-capable.
3.
Prevent dual-interpretation of socket interface DMA handshake signals.
4.
Set the DMA Enable bit.
CL-PD6722
IRQ10
IRQ9
-VPP_VALID
ISA
Bus
DREQ
-DACK
TC