參數(shù)資料
型號： ADUC7032BSTZ-8V-RL
廠商： Analog Devices Inc
文件頁數(shù)： 91/128頁
文件大小： 0K
描述： IC BATTERY SENSOR PREC 48-LQFP
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉換器： A/D 2x16b
振蕩器型： 內部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 標準包裝
其它名稱： ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 65 of 128
A factory or end-of-line calibration for the I-ADC would be a
2-step procedure:
1. Apply 0A current.
Configure the ADC in the required PGA setting etc. and write
to ADCMDE[2:0] to perform a System Zero-Scale Calibration.
This writes a new offset calibration value into ADC0OF.
2. Apply a Full-Scale current for the selected PGA setting.
Write to ADCMDE to perform a System Full-Scale Calibration.
This writes a new gain calibration value into ADC0GN.
Understanding the Offset and Gain Calibration
Registers
The output of the average block in the ADC signal flow
described earlier after the digital filter and before the Offset and
Gain scaling can be considered to be a fractional number with a
span, for a +/- Full-Scale input, of approx +/-0.75. The span is
less than +/-1.0 because there is attenuation in the modulator
to accommodate some over-range capacity on the input signal.
The exact value of the attenuation will vary slightly from part-
to-part, because of manufacturing tolerances.
The Offset Coefficient is read from the ADC0OF calibration
register. This value is a 16-Bit 2's complement number. The
range of this number, in terms of the signal chain, is effectively
+/-1.0. 1 LSB of the ADC0OF register is therefore not the same
as 1LSB of ADC0DAT.
A positive value of ADC0OF indicates that offset is subtracted
from the output of the filter, a negative value is added. The
nominal value of this register is 0x0000, indicating zero offset is
to be removed. The actual offset of the ADC may vary slightly
from part-to-part and at different PGA gains. The offset within
the ADC is minimized if the Chopping mode is active
(ADCFLT[15]=1).
The Gain Coefficient is a unitless scaling factor. The 16-Bit
value in this register is divided by 16384, and then multiplied
by the offset-corrected value. The nominal value of this register
equals 0x5555, which corresponds to a multiplication factor of
1.3333. This scales the nominal +/-0.75 signal to produce a full-
scale output signal of +/-1.0 which is checked for Overflow/
Underflow and converted to Two's Complement or Unipolar
mode as appropriate, before being output to the Data register.
The actual gain, and the required scaling coefficient for zero
gain error, varies slightly from part to part, and at different
PGA settings and in Normal / Low-Power-Mode. The value
downloaded into ADC0GN at power-on/reset represents the
scaling factor for a PGA Gain=1. There will be some level of
gain error if this value is used at different PGA settings. User
code can over-write the calibration coefficients or run ADC
calibrations to correct the gain error at the current PGA setting.
In Summary, the simplified ADC transfer function can be
described as :
ADCGNNOM
ADCGN
ADCOF
VREF
VIN
ADCOUT
*
=
This equation is valid for Voltage/Temperature channel ADC.
For the Current Channel ADC,
ADCGNNOM
ADCGN
ADCOF
K
VREF
VIN
ADCOUT
*
=
where K is dependent on PGA gain setting and ADC mode.
Normal Mode:
For PGA gains of 1,4,8,16,32 and 64 the K factor is 1. For
PGA gains of 2 and 128 the K factor is 2. For PGA gain of 256
the K Factor is 4. For PGA gain of 512, the K factor is 8.
Low Power Mode:
The PGA gain is set to 128 and the K factor is 32.
Low Power Plus Mode:
The K factor is 8.
In Low-Power and Low-Power-Plus Mode, the K factor doubles
if (AVDD_Reg)/2 is used as the reference.
ADC DIAGNOSTICS
The ADuC7032 features diagnostic capability on all three
ADCs.
Current ADC Diagnostics
The ADuC7032 features the capability to detect Open Circuit
conditions on the application board. This is accomplished
using the two current sources on IIN+ and IIN-, which is
controlled via ADC0CON[14,13].
The use of both the IIN+ and IIN- current sources is shown in
Table 33.
To verify the current ADC is converting correctly, it is possible
to select an internal test voltage via ADC0CON[7,6]. Selecting
mode 10 results in the current ADC converting the Voltage
Reference, e.g. The Precision 1.2V Reference, divided by 136 for
PGA settings less than or equal to 128 and divided by
(1.0625*Gain) for PGA settings greater than 128.
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