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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 32 of 128
- FEExPRO (x= 0 or 1): A buffer of the FEEHIDE register,
which is used to store the FEEHIDE value, so it is
automatically downloaded to the FEEHIDE registers on
subsequent reset and power-on events.
NOTE:
User Software must ensure that the Flash/EE memory
controller has completed any Erase or Write cycle
before
the PLL is powered down. If the PLL is
powered down before an Erase or Write cycle is
completed, the Flash/EE page or byte may be
corrupted.
The following sections describe in detail the bit designations of
each of Flash/EE control MMRs
FEE0CON and FEE1CON Registers :
Name :
FEE0CON and FEE1CON
Address :
0xFFFF0E08 and 0xFFFF0E88
Default Value (both registers) :
0x07
Access :
Read/Write Access
Function :
These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for
Block0 (32KB) and Block1 (64KB).
Table 11: Command Codes in FEE0CON and FEE1CON
Code
Command
Description (note x is 0 or 1 to designate Flash/EE Block 0 or 1)
0x00*
Reserved
Reserved, this command should not be written by user code
0x01
*
Single Read
Load FEExDAT with the 16-bit data indexed by FEExADR
0x02
*
Single Write
Write FEExDAT at the address pointed by FEExADR. This operation takes 50
s.
0x03
*
Erase-Write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This
operation takes 20ms
0x04
*
Single Verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the
comparison is returned in FEExSTA bit 1
0x05
*
Single Erase
Erase the page indexed by FEExADR
0x06
*
Mass erase
Erase Block0(30kByte) or Block1(64kByte) of user space. The 2kByte Kernel is protected. This operation
takes 1.2s To prevent accidental execution, a command sequence is required to execute this instruction,
this is described below.
0x07
Default command.
0x08
0x09
Reserved
Reserved, this command should not be written by user code
0x0A
Reserved
Reserved, this command should not be written by user code
0x0B
Signature
FEE0CON:
This command will result in a 24-bit LFSR based signature been generated and loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command will result in a 24 bit LFSR based signature of the user code
space from the page specified in FEE0ADR upwards, including the Kernel, security bits and Flash/EE key.
If FEE0ADR is greater than 0x97800, the Kernel and manufacturing data is signed
FEE1CON:
This command will result in a 24-bit LFSR based signature been generated, beginning at FEE1ADR and
ending at the end of the 63.5k Block, and loaded into FEE1SIG. The last page of this block is not included
in the Sign generation.
0x0C
Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass
erase (0x06) or with the key
0x0D
Reserved
Reserved, this command should not be written by user code
0x0E
Reserved
Reserved, this command should not be written by user code
0x0F
Ping
No operation, interrupt generated
* The FEExCON will always read 0x07 immediately after execution of any of these commands.
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