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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 34 of 128
FEE0MOD and FEE1MOD Registers :
Name :
FEE0MOD and FEE1MOD
Address :
0xFFFF0E04 and 0xFFFF0E84
Default Value (both registers) :
0x00
Access :
Read/Write
Function :
These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers.
Table 13: FEE0MOD and FEE1MOD MMR bit designations
Bit
Description (note: x is 0 or 1 to designate Flash/EE Block 0 or 1)
15-7
Not Used
These bits are reserved for future functionality and should be written as 0 by user code
6, 5
Flash/EE Security Lock Bits
These bits must be written as [6,5] = 1,0 to complete the Flash security protect sequence
4
Flash/EE Controller Command Complete Interrupt Enable
This bit is set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE
command.
This bit is cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
3
Flash/EE Erase/Write Enable
Set by user code to enable the Flash/EE erase and write access via FEExCON
Cleared by user code to disable the Flash/EE erase and write access via FEExCON
2
Reserved and should be written as zero
1
Flash/EE Controller Abort Enable
This bit is set to 1 by user code to enable the Flash/EE controller abort functionality.
0
Reserved and should be written as zero
FLASH/EE MEMORY SECURITY
The 94kByte of Flash/EE memory available to the user can be
read and write protected using the FFE0HID and FEE1HID
registers.
In Block0, the FEE0HID MMR protects the 30kBytes. Bits 0-28
of this register protect pages 0-57 from writing. Each bit
protects 2 pages, i.e. 1kBytes. Bits 29-30 protect pages 58 and 59
respectively, i.e. each bit write protects a single page of 512
bytes. The MSB of this register (Bit31) protects Block0 from
been read via JTAG.
The FEE0PRO register mirrors the bit definitions of the
FEE0HID MMR. The FEE0PRO MMR allows user code to lock
the protection or security configuration of the Flash memory so
that the protection configuration is automatically loaded on
subsequent power-on or reset events. This flexibility allows the
user to set and test protection settings temporarily using the
FEE0HID MMR and subsequently lock the required protection
configuration (using FEE0PRO) when shipping protection
systems into the field.
In Block1 (64K), the FEE1HID MMR protects the 64kBytes.
Bits 0-29 of this register protect pages 0-119 from writing. Each
bit protects 4 pages, i.e. 2kBytes. Bit30 protect pages 120-127,
i.e. bit 30 write protects eight pages of 512 bytes. The MSB of
this register (Bit31) protects Flash/EE Block1, from been read
via JTAG.
As with Block0, FEE1PRO register mirrors the bit definitions of
the FEE1HID MMR. The FEE1PRO MMR is allows user code
to lock the protection or security configuration of the Flash
memory so that the protection configuration is automatically
loaded on subsequent power-on or reset events.
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