參數(shù)資料
型號: ADUC7032BSTZ-8V-RL
廠商: Analog Devices Inc
文件頁數(shù): 77/128頁
文件大?。?/td> 0K
描述: IC BATTERY SENSOR PREC 48-LQFP
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 標準包裝
其它名稱: ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 52 of 128
1, 1, 0 ADC System Zero-Scale Calibration
In this mode, an zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage
driven at the ADC input pins. The calibration is carried out at the user programmed ADC settings, therefore, as with a
normal single ADC conversion, it will take 3 ADC conversion cycles before a fully settled calibration result is ready.
1, 1, 1 ADC System Full-Scale Calibration
In this mode, an full-scale calibration is performed on enabled ADC channels against an external full-scale voltage
driven at the ADC input pins.
Current Channel ADC Control Register :
Name :
ADC0CON
Address :
0xFFFF050C
Default Value :
0x0002
Access :
Read/Write
Function :
The Current Channel ADC Control MMR is an 16-bit register that is used to configure the I-ADC.
Note:
If the Current ADC is reconfigured via ADC0CON, the Voltage and Temperature ADCs are also reset.
Table 24 : ADC0CON MMR Bit Designations
Bit
Description
15
Current Channel ADC Enable
This bit is set to 1 by user code to enable the I-ADC
Clearing this bit to 0, powers down the I-ADC and resets the respective ADC READY bit in the ADCSTA MMR to 0
14, 13
IIN Current Source Enable
0, 0
Current Sources Off
0, 1
Enable 50uA current source on IIN+
1, 0
Enable 50uA current source on IIN-
1, 1
Enable 50uA current source on both IIN- and IIN+
NOTE: These current sources have a tolerance of +-30%. A PGA gain equal to or greater than 2 ( ADC0CON [3-0 ] != 0000 )
must be used when current sources are enabled.
12– 10
Not Used
These bits are reserved for future functionality and should be written as zero
9
Current Channel ADC Output Coding
This bit is set to 1 by user code to configure I-ADC output coding as unipolar
This bit is cleared to 0 by user code to configure I-ADC output coding as 2’s complement
8
Not Used
This bit is reserved for future functionality and should be written as zero
7, 6
Current Channel ADC Input Select
0, 0
IIN+, IIN-
0, 1
IIN-, IIN-
Diagnostic, internal short configuration
1, 0
ADC Reference/136, 0V
Diagnostic, test voltage for gain settings <= 128
ADC Reference/(1.0625XGain), 0V
Diagnostic, test voltage for gain settings > 128
Note: If (REG_AVDD, AGND) divided by 2 Reference is selected, REG_AVDD is used for Vref in this mode. This will
lead to ADC0DAT scaled by two
1, 1
Not Defined
5, 4
Current Channel ADC Reference Select
0, 0
Internal, 1.2V precision reference selected. In ADC Low Power Mode, the Voltage Reference selection is
controlled by ADCMDE[5]
0, 1
External reference inputs (VREF, GND_SW) selected
1, 0
External reference inputs divided by 2 (VREF, GND_SW)/2 selected, this allows an external reference up to
REG_AVDD
1, 1
(REG_AVDD, AGND) divided by 2 selected
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