
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 3 of 128
PLLCON Pre-write Key PLLKEY1: ........................... 70
PLLCON Register : .................................................... 70
POWCON Pre-write Key POWKEY0: ....................... 70
POWCON Pre-write Key POWKEY1: ....................... 70
POWCON Register : .................................................. 71
ADUC7032 LOW POWER CLOCK CALIBRATION ............. 72
OSC0TRM Register :.................................................. 73
OSC0CON Register : ................................................. 73
OSC0STA Register : ................................................... 74
OSC0VAL0 Register :................................................. 74
OSC0VAL1 Register :................................................. 74
PROCESSOR REFERENCE PERIPHERALS ............ 75
INTERRUPT SYSTEM........................................................ 75
TIMERS ........................................................................... 77
TIMER0 – LIFE-TIME TIMER ............................................ 78
Timer0 Value Register : .............................................. 78
Timer0 Capture Register : .......................................... 78
Timer0 Control Register :........................................... 79
Timer0 Load Registers: .............................................. 79
Timer0 Clear Register :.............................................. 79
TIMER1 ........................................................................... 80
Timer1 Load Registers: .............................................. 80
Timer1 Clear Register :.............................................. 80
Timer1 Value Register : .............................................. 80
Timer1 Capture Register : .......................................... 81
Timer1 Control Register :........................................... 81
TIMER2 - WAKE-UP TIMER ............................................. 82
Timer2 Load Registers: .............................................. 82
Timer2 Clear Register :.............................................. 82
Timer2 Value Register : .............................................. 82
Timer2 Control Register :........................................... 83
TIMER3 - WATCHDOG TIMER........................................... 84
Timer3 Load Register :............................................... 84
Timer3 Value Register : .............................................. 84
Timer3 Clear Register :.............................................. 85
Timer3 Control Register :........................................... 85
GENERAL PURPOSE I/O ............................................. 86
GPIO Port0 Control Register : .................................. 88
GPIO Port1 Control Register : .................................. 89
GPIO Port2 Control Register : .................................. 89
GPIO Port0 Data Register :....................................... 90
GPIO Port1 Data Register :....................................... 91
GPIO Port2 Data Register :....................................... 92
GPIO Port0 Set Register :.......................................... 93
GPIO Port1 Set Register :.......................................... 94
GPIO Port2 Set Register :.......................................... 94
GPIO Port0 Clear Register : ..................................... 95
GPIO Port1 Clear Register : ..................................... 95
GPIO Port2 Clear Register : ..................................... 96
HIGH VOLTAGE PERIPHERAL CONTROL
INTERFACE .................................................................... 97
High Voltage Interface Control Register :.................. 98
High Voltage Data Register: ...................................... 99
High Voltage Configuration0 Register : ................... 100
High Voltage Configuration1 Register : ................... 101
High Voltage Interrupt Status Register :................... 102
High Voltage Monitor Register :............................... 103
WAKE-UP(WU).............................................................104
Wake-Up(WU) Pin Circuit Description .................... 104
HANDLING INTERRUPTS FROM THE HIGH VOLTAGE
PERIPHERAL CONTROL INTERFACE................................105
LOW VOLTAGE FLAG ( LVF ).........................................105
HIGH VOLTAGE DIAGNOSTICS.......................................105
UART SERIAL INTERFACE....................................... 106
BAUD RATE GENERATION ..............................................106
Normal 450 UART baud rate generation. ................ 106
ADuC7032 Fractional divider: ................................ 106
UART REGISTER DEFINITION ........................................107
UART TX Register: .................................................. 107
UART RX Register:.................................................. 107
UART Divisor Latch Register 0:............................... 107
UART Divisor Latch Register 1:............................... 107
UART Control Register 0: ....................................... 108
UART Control Register 1: ....................................... 109
UART Status Register 0: .......................................... 109
UART Interrupt Enable Register 0: .......................... 110
UART Interrupt Identification Register 0:................ 110
UART Fractional Divider Register: ..........................111
SERIAL PERIPHERAL INTERFACE ........................ 112
SPI Control Register : .............................................. 113
SPI Status Register : ................................................. 114
SPI Receive Register : .............................................. 114
SPI Transmit Register :............................................. 114
SPI Divider Register : .............................................. 114
LIN (LOCAL INTERCONNECT NETWORK )
INTERFACE .................................................................. 115
LIN MMR DESCRIPTION .............................................. 115
LIN Hardware Synchronization Status Register : ..... 116
LIN Hardware Synchronization Control Register 0: 117
LIN Hardware Synchronization Control Register 1: 118
LIN Hardware Synchronization Timer0 Register : ... 118
LIN Hardware Break Timer1 Register :.................... 119
LIN HARDWARE INTERFACE ......................................... 119
LIN Frame Protocol ................................................. 119
LIN Frame Break Symbol ......................................... 120
LIN Frame Synchronization Byte ............................. 120
LIN Frame Protected Identifier ................................ 120
LIN Frame Data Byte ............................................... 121
LIN Frame Data Transmission and Reception ......... 121
Example LIN Hardware Synchronization Routine.... 122
LIN Diagnostics........................................................ 123
ADUC7032 ON-CHIP DIAGNOSTICS ....................... 124
ADC Diagnostics ...................................................... 124
High Voltage I/O Diagnostics................................... 124
PART IDENTIFICATION ............................................ 125