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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 103/128頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱(chēng)： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 76 of 128
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general purpose interrupt
handling of internal and external events.
The four 32-bit registers dedicated to IRQ are:
- IRQSIG, reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG will be set, otherwise it is cleared. The IRQSIG
bits are cleared when the interrupt in the particular
peripheral is cleared. All IRQ sources can be masked in the
IRQEN MMR. IRQSIG is read-only.
IRQSIG may be used to poll interrupt sources.
- IRQEN, provides the value of the current enable mask. When
bit is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled
or masked which will not create an IRQ exception.
- IRQCLR, (write-only register) allows clearing the IRQEN
register in order to mask an interrupt source. Each bit set to 1
will clear the corresponding bit in the IRQEN register
without affecting the remaining bits. The pair of registers
IRQEN and IRQCLR allows independent manipulation of
the enable mask without requiring an atomic read-modify-
write.
- IRQSTA, (read-only register) provides the current enabled
IRQ source status( effectively a logic AND of the IRQSIG
and IRQEN bits). When set to 1 that source will generate an
active IRQ request to the ARM7TDMI core. There is no
priority encoder or interrupt vector generation. This function
is implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create a single IRQ
signal to the ARM7TDMI core.
FIQ
The FIQ (Fast Interrupt reQuest) is the exception signal to
enter the FIQ mode of the processor. It is provided to service
data transferor communication channel tasks with low latency.
The FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA.
Bit 31 to 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and the bit 0 of both the FIQ and IRQ
registers (FIQ source).
The logic for FIQEN and FIQCLR will not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to ‘1’
in FIQEN will, as a side-effect, clear the same bit in IRQEN. A
bit set to ‘1’ in IRQEN will, as a side-effect, clear the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed interrupts
As the programmed interrupts are non-maskable, they are
controlled by another register, SWICFG, which write into both
IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 42a. This MMR allows the control of
programmed source interrupt.
Table 42 : SWICFG MMR Bit Descriptions
Bit
Description
31-3
Reserved
2
Programmed Interrupt-FIQ
Setting/clearing this bit correspond in setting/clearing
bit 1 of FIQSTA and FIQSIG
1
Programmed Interrupt-IRQ
Setting/clearing this bit correspond in setting/clearing
bit 1 of IRQSTA and IRQSIG
0
Reserved
Note that any interrupt signal must be active for at least the
minimum interrupt latency time, to be detected by the interrupt
controller and to be detected by user in the IRQSTA/FIQSTA
register.
05
99
4-
02
9
IR
QS
TA
FIQS
T
A
IR
QS
IG
FI
Q
S
IG
TIMER0
TIMER1
TIMER2
TIMER3
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQ
IR
QE
N
FI
Q
E
N
TIMER0
TIMER1
TIMER2
TIMER3
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQ
IRQ
FIQ
Figure 29: Interrupt Structure
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