參數(shù)資料
型號： ADUC7032BSTZ-8V-RL
廠商： Analog Devices Inc
文件頁數(shù)： 4/128頁
文件大?。?/td> 0K
描述： IC BATTERY SENSOR PREC 48-LQFP
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 標準包裝
其它名稱： ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 101 of 128
High Voltage Configuration1 Register :
Name :
HVCFG1
Address :
Indirectly addressed via the HVCON high voltage interface
Default Value :
0x00
Access :
Read/Write
Function :
This 8-bit register controls the function of high voltage circuits on the ADuC7032. This register is not an MMR and
does not appear in the MMR memory map. It is accessed via the HVCON registered interface, data to be written to
this register is loaded via HVDAT and data is read back from this register via HVDAT.
Table 65: HVCFG1 Bit Designations
Bit
Description
7
Attenuator Enable Bit
This bit is cleared to 0 to disable the internal voltage attenuator and attenuator buffer.
This bit is set to 1 to enable the internal voltage attenuator and attenuator buffer.
6
High Voltage Temperature Monitor
The high voltage temperature monitor is an un-calibrated temperature monitor located on-chip close to the high voltage
circuits. This monitor is completely separate to the on-chip, precision temperature sensor(controlled via ADC2CON[7,6])
and allows user code to monitor die temperature change close the hottest part of the ADuC7032 die. The monitor
generates a typical output voltage of 600mV at 25
°C and has a negative temperature coefficient of typically -2.1mV/°C
This bit is set to 1 to enable the on-chip, high voltage temperature monitor. Once enabled this voltage out temperature
monitor is routed directly to the temperature channel ADC.
This bit is cleared to 0 to disable the on-chip, high voltage temperature monitor.
5
Voltage Channel Short Enable Bit
This bit is set to 1 to enable an internal short (at the attenuator, before ADC input buffer) on the voltage channel ADC and
allow noise be measured as a self diagnostic test.
This bit is cleared to 0 to disable an internal short on the voltage channel.
4
WU Read Back Enable Bit
This bit is cleared to 0 to disable input capability on the external WU pin
This bit is set to 1 to enable input capability on the external WU pin. In this mode, a rising or falling edge transition on the
WU pin will generate a high voltage interrupt. Once this bit is set, the state of the WU pin can be monitored via the
HVMON register (HVMON[7]).
3
HV-IO Enable Bit
This bit is set to 1 to re-enable any High Voltage-IO pins (LIN/Wake) that have been disabled as a result of an short circuit
current event(event must last longer than 20usecs for LIN Pin and 400usecs for Wake Pin).
This bit must also be set to 1 to re-enable the Wake pin if disabled by a thermal event.
It should be noted that this bit must be set to clear any pending interrupt generated by the short circuit event (even if the
event has passed) as well as re-enabling the High-Voltage IO pins.
2
Enable/Disable Short Circuit Protection (LIN)
This bit is set to 1 to enable ‘passive’ short circuit protection on LIN pin. In this mode, a short circuit event on the LIN pin
will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA but will NOT disable the short
circuiting pin.
This bit is cleared to 0 to enable ‘a(chǎn)ctive’ short circuit protection on LIN pin. In this mode, a short circuit event the LIN pin
will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA and automatically disable the
short circuiting pin. Once disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3].
1
WU Pin Time-Out ( MonoFlop ) Counter Enable/Disable
This bit is set to disable the WU I/O time-out counter.
This bit is cleared to enable a time-out counter which automatically de-asserts the WU pin 1.3 seconds after user code
has asserted the WU pin via HVCFG0[4].
0
WU O/C Diagnostic Enable
This bit is set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin thus allowing detection of an O/C
condition on the WU pin.
This bit is cleared to disable an internal WU I/O diagnostic pull-up resistor
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