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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 117 of 128
LIN Hardware Synchronization Control Register 0:
Name :
LHSCON0
Address :
0xFFFF0784
Default Value :
0x0000
Access :
Read/Write
Function :
The LHS Control register is a 16-bit register that in conjunction with the LHSCON1 register is used to configure the
LIN mode of operation.
Table 82 : LHSCON0 MMR Bit Descriptions
Bit
Description
15-12
Reserved
These bits are reserved for future and should be written as 0 by user software.
11
Break Timer Compare Interrupt Disable:
This bit is set to 1 to disable the Break Timer Compare interrupt.
This bit is cleared to 0 to enable the Break Timer Compare Interrupt
10
Break Timer Error Interrupt Disable:
This bit is set to 1 to disable the Break Timer Error interrupt.
This bit is cleared to 0 to enable the Break Timer Error Interrupt
9
LIN Transceiver, Stand-Alone Test Mode
This bit is cleared to 0 by user code to operate the LIN in normal mode, driven directly from the on-chip UART.
This bit is set to 1 by user code to enable external GPIO7 and GPIO8 pins to drive the LIN transceiver TxD and RxD
respectively, independent of the UART. The functions of GPIO7 and GPIO8 should first be configured by user code via
GPIO function select bits <0 and 4> in the GP2CON register.
8
Gate UART
Bit
This bit is set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break field
and subsequent LIN Sync byte have been detected. This ensures the UART will not receive any spurious serial data during
Break or Sync field periods which will have to be flushed out of the UART before valid data fields can start to be received.
This bit is set to 0 by user code to enable the internal UART RxD (receive data) after the break field and subsequent LIN
Sync byte have been detected so that the UART can receive the subsequent LIN data fields.
7
Sync Timer Stop Edge Type Bit
This bit is cleared to 0 by user code to stop the sync timer on the falling edge count configured via the LHSCON1[7:4]
register.
This bit is set to 1 by user code to stop the sync timer on the rising edge count configured via the LHSCON1[7:4] register.
6-5
Reserved
These bits are reserved for future and should be written as 0 by user software.
4
Enable Stop Interrupt
This bit is cleared to 0 by user code to disable interrupts when a stop condition occurs
This bit is set to 1 by user code to generate an interrupt when a stop condition occurs
3
Enable Start Interrupt
This bit is cleared to 0 by user code to disable interrupts when a start condition occurs
This bit is set to 1 by user code to generate an interrupt when a start condition occurs
2
LIN Sync Enable Bit
This bit is cleared to 0 by user code to disable LHS functionality
This bit is set to 1 by user code to enable LHS functionality
1
Edge Counter Clear Bit
This bit is cleared to 0 by user code to enable the rising or falling edge counters to function normally
This bit is set to 1 by user code to clear the internal edge counters in the LHS peripheral, this bit does not reset to 0
automatically and requires user code to write 0 to re-enable the edge counters.
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