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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/128頁 |
| 文件大小： | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 49 of 128
ADC MMR INTERFACE
The ADC is controlled and configured via a number of MMRs that are described in detail in the following pages:
ADC Status Register :
Name :
ADCSTA
Address :
0xFFFF0500
Default Value :
0x0000
Access :
Read Only
Function :
This read only register holds general status information related to the mode of operation or current status of the
ADuC7032ADCs.
Table 22 : ADCSTA MMR Bit Designations
Bit
Description
15
ADC Calibration Status
This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed.
This bit is cleared after ADCMDE is written to.
14
ADC Temperature Conversion Error
This bit is set automatically in hardware to indicate that a temperature conversion over-range or under-range has occurred.
The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this
case.
This bit will be cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
13
ADC Voltage Conversion Error
This bit is set automatically in hardware to indicate that a voltage conversion over-range or under-range has occurred. The
conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case.
This bit will be cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC Current Conversion Error
This bit is set automatically in hardware to indicate that an a current conversion over-range or under-range has occurred. The
conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case.
This bit will be cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
11
Not Used
This bit is reserved for future functionality and should not be monitored by user code
10
Not Used
This bit is reserved for future functionality and should not be monitored by user code
9
ADCFIFO Error Flag
This bit is set to 1 automatically to indicate that the FIFO has overflowed. This bit does not cause an interrupt but is latched
high and can only be cleared by disabling the FIFO or reconfiguring the ADC.
This bit will read 0 is the FIFO is disabled or if the FIFO has not overflowed.
8
ADC FIFO Empty Flag
This bit is set to 1 automatically to indicate the ADC FIFO is empty. It is a flag bit only and cannot generate an interrupt.
This bit reads 0 if the ADC FIFO is disabled.
7
ADC FIFO Full Flag
This bit is set to 1 automatically to indicate the ADC FIFO is full and any subsequent I and V ADC conversion results will
overflow and corrupt the ADC FIFO.
This bit is cleared by disabling the FIFO or reconfiguring the ADC.
6
Accumulator Comparator Threshold Exceeded
This bit indicates that the absolute value of the Current Channel Accumulator has exceeded the programmed threshold.
This bit is cleared by disabling the Accumulator Comparator function in ADCCFG[6,5] or by reconfiguring the ADC.
5
Not Used
This bit is reserved for future functionality and should not be monitored by user code
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