參數(shù)資料
型號: ADUC7032BSTZ-8V-RL
廠商: Analog Devices Inc
文件頁數(shù): 64/128頁
文件大小: 0K
描述: IC BATTERY SENSOR PREC 48-LQFP
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 標準包裝
其它名稱: ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 40 of 128
MEMORY MAPPED REGISTERS
The Memory Mapped Register (MMR) space is mapped into
the top 4kBytes of the MCU memory space and accessed by
indirect addressing, load and store commands, through the
ARM7 banked registers. An outline of the ADuC7032s Memory
Mapped Register Bank is shown in Figure 14.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core
registers (described in ARM Registers) reside in the MMR area.
As can be seen from the detailed MMR map in Table 17, the
MMR data widths vary from 1 Byte (8 bits) to 4 Bytes (32 bits).
The ARM7 core can access any of the MMRs (single byte or
multiple byte width registers) with a 32 bit read or write access.
The resultant read for example, aligned per ‘little endian’
format described earlier. However, errors will result if the
ARM7 core tries to access 4 Byte (32 bit) MMRs with a 16-bit
access. In the case of a (16-bit) write access to a 32-bit MMR,
the (upper) 16 most significant bits will be written as 0’s. More
obviously, in the case of a 16-bit read access to a 32-bit MMR,
only 16 of the MMR bits can be read.
FLASH CONTROL
INTERFACE
GPIO
SPI
SERIAL TEST
INTERFACE
HV INTERFACE
LIN/BSD
HARDWARE
UART
ADC
PLL AND
OSCILLATOR CONTROL
GENERAL PURPOSE
TIMER 4
WATCHDOG
TIMER 3
WAKE UP
TIMER 2
GENERAL PURPOSE
TIMER 1
TIMER 0
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
0xFFFFFFFF
0xFFFF1000
0xFFFF0E00
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF0894
0xFFFF0880
0xFFFF0810
0xFFFF0800
0xFFFF079C
0xFFFF0780
0xFFFF0730
0xFFFF0700
0xFFFF0568
0xFFFF0500
0xFFFF044C
0xFFFF0400
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0244
0xFFFF0220
0xFFFF0110
0xFFFF0000
05
99
4-
014
Figure 14: Top Level MMR Map
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