參數(shù)資料
型號: ADUC7032BSTZ-8V-RL
廠商: Analog Devices Inc
文件頁數(shù): 23/128頁
文件大?。?/td> 0K
描述: IC BATTERY SENSOR PREC 48-LQFP
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 標準包裝
其它名稱: ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 119 of 128
LIN Hardware Break Timer1 Register :
Name :
LHSVAL1
Address :
0xFFFF0790
Default Value :
0x000(read) or 0x047(write)
Access :
Read/Write
Function :
When user code reads this location, the 12-bit value returned is the value of the internal LIN break timer, which is
clocked directly from the on-chip low power (131KHz) oscillator and times the LIN Break pulse. A negative edge on
the LIN bus or user code reading the LHSVAL1 will result in the timer and the register contents being reset to 0.
When user code writes to this location, the 12-bit value is actually written not to the LIN Break timer but to a LIN
Break Compare register.
In LIN mode of operation the value in the compare register is continuously compared to the break timer value. A LIN
Break interrupt (IRQEN[7] and LHSSTA[0]) is generated when the timer value reaches the compare value. After the
Break Condition interrupt, the LIN Break timer continues to count until the rising edge of the Break signal. If a
rising edge is not detected and the 12-bit timer overflows (4096 X 1/131KHz= 31msecs), a Break Field Error Interrupt
(IRQEN[7] and LHSSTA[4]) will be generated. By default, the value in the compare register is 0x47, this corresponds
to 11 X Bit periods i.e. the minimum pulse width for a LIN break pulse at 20kbps. For different baud rates, this value
may be changed by writing to. It is also important to note that if a valid break interrupt is not received then
subsequent Sync pulse timing via LHSVAL0 register will not occur.
LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is broken into 4 main categories:
Break Symbol
SYNC Byte
Protected Identifier
Data Bytes
The format of the frame header, Break, Synchronization Byte
and Protected Identifier are shown in Figure 39. Essentially, the
embedded UART, LIN Hardware Synchronization logic and the
high voltage transceiver interface all combine on-chip to
support and manage LIN based transmissions and receptions.
05
99
4-
04
2
13TBIT
2TBIT
>1TBIT
> = 14TBIT
8TBIT
BREAK
SYNC
STA S0
S1
S2
S3
S4
S5
S6
S7 STO
PROTECTED ID
Figure 39 : LIN Interface Timing
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