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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 119/128頁 |
| 文件大小： | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 90 of 128
16
GPIO11 Function Select Bit
This bit is cleared to 0 by user code to internally disable the LIN input data path. In this configuration GPIO11 is used to
support diagnostic read-back on all external high-voltage I/O pins (see HVCFG1[2:0])
This bit is set to 1 by user code to route input data from the LIN interface to both the LIN hardware
timing/synchronization logic and to the UART RxD (receive data). This mode must be configured by user code when
using LIN .
15-5
Reserved
These bits are reserved and should be written as 0 by user code
4
GPIO8 Function Select Bit
This bit is cleared by user code to 0 to configure the GPIO8 pin as a General Purpose I/O (GPIO) pin
This bit is set by user code to 1 to route the LIN input data to the GPIO8 pin. This mode can be used to drive the LIN
transceiver interface as a standalone component without any interaction from MCU or UART.
3-1
Reserved
These bits are reserved and should be written as 0 by user code
0
GPIO7 Function Select Bi
This bit is cleared by user code to 0 to configure the GPIO7 pin as a General Purpose I/O (GPIO) pin
This bit is set by user code to 1 to route data driven into the GPIO7 pin through the on-chip LIN transceiver to be output
at the LIN pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any
interaction from MCU or UART.
GPIO Port0 Data Register :
Name :
GP0DAT
Address :
0xFFFF0D20
Default Value :
0x00000000
Access :
Read/Write
Function :
This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 48). This register also sets
the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 52 : GP0DAT MMR Bit Descriptions
Bit
Description
31-29
Reserved
These bits are reserved and should be written as 0 by user code
28
Port 0.4 Direction Select Bit
This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.4 as an input.
This bit is set to 1 by user code to configure the GPIO pin assigned to P0.4 as an output.
27
Port 0.3 Direction Select Bit
This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.3 as an input.
This bit is set to 1 by user code to configure the GPIO pin assigned to P0.3 as an output.
26
Port 0.2 Direction Select Bit
This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.2 as an input.
This bit is set to 1 by user code to configure the GPIO pin assigned to P0.2 as an output.
25
Port 0.1 Direction Select Bit
This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.1 as an input.
This bit is set to 1 by user code to configure the GPIO pin assigned to P0.1 as an output.
24
Port 0.0 Direction Select Bit
This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.0 as an input.
This bit is set to 1 by user code to configure the GPIO pin assigned to P0.0 as an output.
23-21
Reserved
These bits are reserved and should be written as 0 by user code
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