
CHAPTER 18 IEBus CONTROLLER
User’s Manual U17790EJ2V0UD
689
(14) IEBus field status register (FSR)
The FSR register stores the status of the field status of the IEBus controller if an interrupt request signal
(INTIE1, INTIE2, INTSTA, or INTERR) is generated.
This register is read-only, in 8-bit units.
Reset sets this register to 00H.
Cautions 1. If an interrupt request signal is generated during communication between third parties,
the FSR register is cleared to 00H. However, because only an interrupt request signal
that is generated if an error occurs is generated during communication between third
parties, the error can be identified as that during communication between third parties,
by reading third-party error flag (ESR.DEFLAG bit).
2. The FSR register updates the status information when an interrupt request signal is
generated. If the FSR register is read at this time, however, an undefined value is read.
3. If another interrupt request signal is generated before the FSR register is read, the status
information when the preceding interrupt occurred is updated by the status information
when the new interrupt occurs.
4. Use the FSR register only for problem analysis; do not use it with the actual software.
0
FSR
0
00
FSTATE1 FSTATE0
After reset: 00H
R
Address: FFFFF371H
65
43
2
1
0
7
Remark
For the explanation of the FSTATE1 and FSTATE0 bits, see Table 18-15 Field Status.
Table 18-15. Field Status
Explanation
Field Status
Master/Slave
Field
Transmission/Reception
Start field
Master address field
Slave address field
Control data field
Telegraph length field
Slave transmission status
FSR = 00H
Slave operation
Data field
Reception
Telegraph length field
Slave transmission status
FSR = 01H
Slave operation
Data field
Transmission
Telegraph length field
Master reception status
FSR = 02H
Master operation
Data field
Reception
Start field
Master address field
Slave address field
Control data field
Telegraph length field
Master transmission status
FSR = 03H
Master operation
Data field
Transmission